1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm-offsets.h>
8 #include <clock_legacy.h>
9 #include <mpc83xx.h>
10 #include <system-constants.h>
11 #include <time.h>
12 #include <asm/global_data.h>
13 
14 #include "lblaw/lblaw.h"
15 #include "elbc/elbc.h"
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 /*
20  * Breathe some life into the CPU...
21  *
22  * Set up the memory map,
23  * initialize a bunch of registers,
24  * initialize the UPM's
25  */
cpu_init_f(volatile immap_t * im)26 void cpu_init_f (volatile immap_t * im)
27 {
28 	/* Pointer is writable since we allocated a register for it */
29 	gd = (gd_t *)SYS_INIT_SP_ADDR;
30 
31 	/* global data region was cleared in start.S */
32 
33 	/* system performance tweaking */
34 
35 #ifndef CONFIG_ACR_PIPE_DEP_UNSET
36 	/* Arbiter pipeline depth */
37 	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
38 			  CONFIG_ACR_PIPE_DEP;
39 #endif
40 
41 #ifndef CONFIG_ACR_RPTCNT_UNSET
42 	/* Arbiter repeat count */
43 	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
44 			  CONFIG_ACR_RPTCNT;
45 #endif
46 
47 #ifdef CONFIG_SYS_SPCR_OPT
48 	/* Optimize transactions between CSB and other devices */
49 	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
50 			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
51 #endif
52 
53 	/* Enable Time Base & Decrementer (so we will have udelay()) */
54 	im->sysconf.spcr |= SPCR_TBEN;
55 
56 	/* DDR control driver register */
57 #ifdef CFG_SYS_DDRCDR
58 	im->sysconf.ddrcdr = CFG_SYS_DDRCDR;
59 #endif
60 	/* Output buffer impedance register */
61 #ifdef CFG_SYS_OBIR
62 	im->sysconf.obir = CFG_SYS_OBIR;
63 #endif
64 
65 	/*
66 	 * Memory Controller:
67 	 */
68 
69 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
70 	 * addresses - these have to be modified later when FLASH size
71 	 * has been determined
72 	 */
73 
74 #if defined(CFG_SYS_NAND_BR_PRELIM)  \
75 	&& defined(CFG_SYS_NAND_OR_PRELIM) \
76 	&& defined(CFG_SYS_NAND_LBLAWBAR_PRELIM) \
77 	&& defined(CFG_SYS_NAND_LBLAWAR_PRELIM)
78 	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
79 	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
80 	im->sysconf.lblaw[0].bar = CFG_SYS_NAND_LBLAWBAR_PRELIM;
81 	im->sysconf.lblaw[0].ar = CFG_SYS_NAND_LBLAWAR_PRELIM;
82 #else
83 #error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CFG_SYS_NAND_LBLAWBAR_PRELIM & CFG_SYS_NAND_LBLAWAR_PRELIM must be defined
84 #endif
85 }
86 
87 /*
88  * Get timebase clock frequency (like cpu_clk in Hz)
89  */
get_tbclk(void)90 unsigned long get_tbclk(void)
91 {
92 	return (gd->bus_clk + 3L) / 4L;
93 }
94 
puts(const char * str)95 void puts(const char *str)
96 {
97 	while (*str)
98 		putc(*str++);
99 }
100 
get_bus_freq(ulong dummy)101 ulong get_bus_freq(ulong dummy)
102 {
103 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
104 	u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
105 
106 	return get_board_sys_clk() * spmf;
107 }
108