1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 */
10
11 #include <config.h>
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <clock_legacy.h>
15 #include <display_options.h>
16 #include <init.h>
17 #include <irq_func.h>
18 #include <log.h>
19 #include <time.h>
20 #include <vsprintf.h>
21 #include <watchdog.h>
22 #include <command.h>
23 #include <fsl_esdhc.h>
24 #include <asm/cache.h>
25 #include <asm/global_data.h>
26 #include <asm/io.h>
27 #include <asm/mmu.h>
28 #include <fsl_ifc.h>
29 #include <asm/fsl_law.h>
30 #include <asm/fsl_lbc.h>
31 #include <post.h>
32 #include <asm/processor.h>
33 #include <fsl_ddr_sdram.h>
34 #include <asm/ppc.h>
35 #include <linux/delay.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 /*
40 * Default board reset function
41 */
42 static void
__board_reset(void)43 __board_reset(void)
44 {
45 /* Do nothing */
46 }
47 void board_reset_prepare(void) __attribute__((weak, alias("__board_reset")));
48 void board_reset(void) __attribute__((weak, alias("__board_reset")));
49 void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
50
checkcpu(void)51 int checkcpu (void)
52 {
53 sys_info_t sysinfo;
54 uint pvr, svr;
55 uint ver;
56 uint major, minor;
57 struct cpu_type *cpu;
58 char buf1[32], buf2[32];
59 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
60 defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
61 ccsr_gur_t __iomem *gur =
62 (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
63 #endif
64
65 /*
66 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
67 * mode. Previous platform use ddr ratio to do the same. This
68 * information is only for display here.
69 */
70 #ifdef CONFIG_FSL_CORENET
71 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
72 u32 ddr_sync = 0; /* only async mode is supported */
73 #else
74 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
75 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
76 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
77 #else /* CONFIG_FSL_CORENET */
78 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
79 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
80 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
81 #else
82 u32 ddr_ratio = 0;
83 #endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
84 #endif /* CONFIG_FSL_CORENET */
85
86 unsigned int i, core, nr_cores = cpu_numcores();
87 u32 mask = cpu_mask();
88
89 #ifdef CONFIG_HETROGENOUS_CLUSTERS
90 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
91 u32 dsp_mask = cpu_dsp_mask();
92 #endif
93
94 svr = get_svr();
95 major = SVR_MAJ(svr);
96 minor = SVR_MIN(svr);
97
98 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
99 if (SVR_SOC_VER(svr) == SVR_T4080) {
100 ccsr_rcpm_t *rcpm =
101 (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
102
103 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
104 FSL_CORENET_DEVDISR2_DTSEC1_9);
105 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
106 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
107
108 /* It needs SW to disable core4~7 as HW design sake on T4080 */
109 for (i = 4; i < 8; i++)
110 cpu_disable(i);
111
112 /* request core4~7 into PH20 state, prior to entering PCL10
113 * state, all cores in cluster should be placed in PH20 state.
114 */
115 setbits_be32(&rcpm->pcph20setr, 0xf0);
116
117 /* put the 2nd cluster into PCL10 state */
118 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
119 }
120 #endif
121
122 if (cpu_numcores() > 1) {
123 #ifndef CONFIG_MP
124 puts("Unicore software on multiprocessor system!!\n"
125 "To enable mutlticore build define CONFIG_MP\n");
126 #endif
127 volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
128 printf("CPU%d: ", pic->whoami);
129 } else {
130 puts("CPU: ");
131 }
132
133 cpu = gd->arch.cpu;
134
135 puts(cpu->name);
136 if (IS_E_PROCESSOR(svr))
137 puts("E");
138
139 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
140
141 pvr = get_pvr();
142 ver = PVR_VER(pvr);
143 major = PVR_MAJ(pvr);
144 minor = PVR_MIN(pvr);
145
146 printf("Core: ");
147 switch(ver) {
148 case PVR_VER_E500_V1:
149 puts("e500v1");
150 break;
151 case PVR_VER_E500_V2:
152 puts("e500v2");
153 break;
154 case PVR_VER_E500MC:
155 puts("e500mc");
156 break;
157 case PVR_VER_E5500:
158 puts("e5500");
159 break;
160 case PVR_VER_E6500:
161 puts("e6500");
162 break;
163 default:
164 puts("Unknown");
165 break;
166 }
167
168 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
169
170 if (nr_cores > CONFIG_MAX_CPUS) {
171 panic("\nUnexpected number of cores: %d, max is %d\n",
172 nr_cores, CONFIG_MAX_CPUS);
173 }
174
175 get_sys_info(&sysinfo);
176
177 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
178 if (sysinfo.diff_sysclk == 1)
179 puts("Single Source Clock Configuration\n");
180 #endif
181
182 puts("Clock Configuration:");
183 for_each_cpu(i, core, nr_cores, mask) {
184 if (!(i & 3))
185 printf ("\n ");
186 printf("CPU%d:%-4s MHz, ", core,
187 strmhz(buf1, sysinfo.freq_processor[core]));
188 }
189
190 #ifdef CONFIG_HETROGENOUS_CLUSTERS
191 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
192 if (!(j & 3))
193 printf("\n ");
194 printf("DSP CPU%d:%-4s MHz, ", j,
195 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
196 }
197 #endif
198
199 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
200 printf("\n");
201
202 #ifdef CONFIG_FSL_CORENET
203 if (ddr_sync == 1) {
204 printf(" DDR:%-4s MHz (%s MT/s data rate) "
205 "(Synchronous), ",
206 strmhz(buf1, sysinfo.freq_ddrbus/2),
207 strmhz(buf2, sysinfo.freq_ddrbus));
208 } else {
209 printf(" DDR:%-4s MHz (%s MT/s data rate) "
210 "(Asynchronous), ",
211 strmhz(buf1, sysinfo.freq_ddrbus/2),
212 strmhz(buf2, sysinfo.freq_ddrbus));
213 }
214 #else
215 switch (ddr_ratio) {
216 case 0x0:
217 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
218 strmhz(buf1, sysinfo.freq_ddrbus/2),
219 strmhz(buf2, sysinfo.freq_ddrbus));
220 break;
221 case 0x7:
222 printf(" DDR:%-4s MHz (%s MT/s data rate) "
223 "(Synchronous), ",
224 strmhz(buf1, sysinfo.freq_ddrbus/2),
225 strmhz(buf2, sysinfo.freq_ddrbus));
226 break;
227 default:
228 printf(" DDR:%-4s MHz (%s MT/s data rate) "
229 "(Asynchronous), ",
230 strmhz(buf1, sysinfo.freq_ddrbus/2),
231 strmhz(buf2, sysinfo.freq_ddrbus));
232 break;
233 }
234 #endif
235
236 #if defined(CONFIG_FSL_LBC)
237 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
238 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
239 } else {
240 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
241 sysinfo.freq_localbus);
242 }
243 #endif
244
245 #if defined(CONFIG_FSL_IFC)
246 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
247 #endif
248
249 #ifdef CONFIG_QE
250 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
251 #endif
252
253 #if defined(CONFIG_SYS_CPRI)
254 printf(" ");
255 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
256 #endif
257
258 #if defined(CONFIG_SYS_MAPLE)
259 printf("\n ");
260 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
261 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
262 printf("MAPLE-eTVPE:%-4s MHz\n",
263 strmhz(buf1, sysinfo.freq_maple_etvpe));
264 #endif
265
266 #ifdef CONFIG_SYS_DPAA_FMAN
267 for (i = 0; i < CFG_SYS_NUM_FMAN; i++) {
268 printf(" FMAN%d: %s MHz\n", i + 1,
269 strmhz(buf1, sysinfo.freq_fman[i]));
270 }
271 #endif
272
273 #ifdef CONFIG_SYS_DPAA_QBMAN
274 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
275 #endif
276
277 #ifdef CONFIG_SYS_DPAA_PME
278 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
279 #endif
280
281 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
282
283 #ifdef CONFIG_FSL_CORENET
284 /* Display the RCW, so that no one gets confused as to what RCW
285 * we're actually using for this boot.
286 */
287 puts("Reset Configuration Word (RCW):");
288 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
289 u32 rcw = in_be32(&gur->rcwsr[i]);
290
291 if ((i % 4) == 0)
292 printf("\n %08x:", i * 4);
293 printf(" %08x", rcw);
294 }
295 puts("\n");
296 #endif
297
298 return 0;
299 }
300
301
302 /* ------------------------------------------------------------------------- */
303
do_reset(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])304 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
305 {
306 /* Everything after the first generation of PQ3 parts has RSTCR */
307 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
308 unsigned long val, msr;
309
310 /*
311 * Initiate hard reset in debug control register DBCR0
312 * Make sure MSR[DE] = 1. This only resets the core.
313 */
314 msr = mfmsr ();
315 msr |= MSR_DE;
316 mtmsr (msr);
317
318 val = mfspr(DBCR0);
319 val |= 0x70000000;
320 mtspr(DBCR0,val);
321 #else
322 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
323
324 /* Call board-specific preparation for reset */
325 board_reset_prepare();
326
327 /* Attempt board-specific reset */
328 board_reset();
329
330 /* Next try asserting HRESET_REQ */
331 out_be32(&gur->rstcr, 0x2);
332 udelay(100);
333
334 /* Attempt last-stage board-specific reset */
335 board_reset_last();
336 #endif
337
338 return 1;
339 }
340
341
342 /*
343 * Get timebase clock frequency
344 */
get_tbclk(void)345 __weak unsigned long get_tbclk(void)
346 {
347 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
348
349 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
350 }
351
352
353 #ifndef CONFIG_WDT
354 #if defined(CONFIG_WATCHDOG)
355 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
356 void
init_85xx_watchdog(void)357 init_85xx_watchdog(void)
358 {
359 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
360 TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC));
361 }
362
363 void
reset_85xx_watchdog(void)364 reset_85xx_watchdog(void)
365 {
366 /*
367 * Clear TSR(WIS) bit by writing 1
368 */
369 mtspr(SPRN_TSR, TSR_WIS);
370 }
371
372 void
watchdog_reset(void)373 watchdog_reset(void)
374 {
375 int re_enable = disable_interrupts();
376
377 reset_85xx_watchdog();
378 if (re_enable)
379 enable_interrupts();
380 }
381 #endif /* CONFIG_WATCHDOG */
382 #endif
383
384 /*
385 * Initializes on-chip MMC controllers.
386 * to override, implement board_mmc_init()
387 */
cpu_mmc_init(struct bd_info * bis)388 int cpu_mmc_init(struct bd_info *bis)
389 {
390 #ifdef CONFIG_FSL_ESDHC
391 return fsl_esdhc_mmc_init(bis);
392 #else
393 return 0;
394 #endif
395 }
396
397 /*
398 * Print out the state of various machine registers.
399 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
400 * parameters for IFC and TLBs
401 */
print_reginfo(void)402 void print_reginfo(void)
403 {
404 print_tlbcam();
405 #ifdef CONFIG_FSL_LAW
406 print_laws();
407 #endif
408 #if defined(CONFIG_FSL_LBC)
409 print_lbc_regs();
410 #endif
411 #ifdef CONFIG_FSL_IFC
412 print_ifc_regs();
413 #endif
414
415 }
416
417 /* Common ddr init for non-corenet fsl 85xx platforms */
418 #ifndef CONFIG_FSL_CORENET
419 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
420 !defined(CFG_SYS_INIT_L2_ADDR)
dram_init(void)421 int dram_init(void)
422 {
423 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
424 defined(CONFIG_ARCH_QEMU_E500)
425 gd->ram_size = fsl_ddr_sdram_size();
426 #else
427 gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024;
428 #endif
429
430 return 0;
431 }
432 #else /* CONFIG_SYS_RAMBOOT */
dram_init(void)433 int dram_init(void)
434 {
435 phys_size_t dram_size = 0;
436
437 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
438 {
439 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
440 unsigned int x = 10;
441 unsigned int i;
442
443 /*
444 * Work around to stabilize DDR DLL
445 */
446 out_be32(&gur->ddrdllcr, 0x81000000);
447 asm("sync;isync;msync");
448 udelay(200);
449 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
450 setbits_be32(&gur->devdisr, 0x00010000);
451 for (i = 0; i < x; i++)
452 ;
453 clrbits_be32(&gur->devdisr, 0x00010000);
454 x++;
455 }
456 }
457 #endif
458
459 #if defined(CONFIG_SPD_EEPROM) || \
460 defined(CONFIG_DDR_SPD) || \
461 defined(CONFIG_SYS_DDR_RAW_TIMING)
462 dram_size = fsl_ddr_sdram();
463 #else
464 dram_size = fixed_sdram();
465 #endif
466 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
467 dram_size *= 0x100000;
468
469 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
470 /*
471 * Initialize and enable DDR ECC.
472 */
473 ddr_enable_ecc(dram_size);
474 #endif
475
476 #if defined(CONFIG_FSL_LBC)
477 /* Some boards also have sdram on the lbc */
478 lbc_sdram_init();
479 #endif
480
481 debug("DDR: ");
482 gd->ram_size = dram_size;
483
484 return 0;
485 }
486 #endif /* CONFIG_SYS_RAMBOOT */
487 #endif
488
489 #if CFG_POST & CFG_SYS_POST_MEMORY
490
491 /* Board-specific functions defined in each board's ddr.c */
492 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
493 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
494 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
495 phys_addr_t *rpn);
496 unsigned int
497 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
498
499 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
500
dump_spd_ddr_reg(void)501 static void dump_spd_ddr_reg(void)
502 {
503 int i, j, k, m;
504 u8 *p_8;
505 u32 *p_32;
506 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
507 generic_spd_eeprom_t
508 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
509
510 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
511 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
512
513 puts("SPD data of all dimms (zero value is omitted)...\n");
514 puts("Byte (hex) ");
515 k = 1;
516 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
517 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
518 printf("Dimm%d ", k++);
519 }
520 puts("\n");
521 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
522 m = 0;
523 printf("%3d (0x%02x) ", k, k);
524 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
525 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
526 p_8 = (u8 *) &spd[i][j];
527 if (p_8[k]) {
528 printf("0x%02x ", p_8[k]);
529 m++;
530 } else
531 puts(" ");
532 }
533 }
534 if (m)
535 puts("\n");
536 else
537 puts("\r");
538 }
539
540 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
541 switch (i) {
542 case 0:
543 ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
544 break;
545 #if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
546 case 1:
547 ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
548 break;
549 #endif
550 #if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
551 case 2:
552 ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
553 break;
554 #endif
555 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
556 case 3:
557 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
558 break;
559 #endif
560 default:
561 printf("%s unexpected controller number = %u\n",
562 __func__, i);
563 return;
564 }
565 }
566 printf("DDR registers dump for all controllers "
567 "(zero value is omitted)...\n");
568 puts("Offset (hex) ");
569 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
570 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
571 puts("\n");
572 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
573 m = 0;
574 printf("%6d (0x%04x)", k * 4, k * 4);
575 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
576 p_32 = (u32 *) ddr[i];
577 if (p_32[k]) {
578 printf(" 0x%08x", p_32[k]);
579 m++;
580 } else
581 puts(" ");
582 }
583 if (m)
584 puts("\n");
585 else
586 puts("\r");
587 }
588 puts("\n");
589 }
590
591 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
reset_tlb(phys_addr_t p_addr,u32 size,phys_addr_t * phys_offset)592 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
593 {
594 u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
595 unsigned long epn;
596 u32 tsize, valid, ptr;
597 int ddr_esel;
598
599 clear_ddr_tlbs_phys(p_addr, size>>20);
600
601 /* Setup new tlb to cover the physical address */
602 setup_ddr_tlbs_phys(p_addr, size>>20);
603
604 ptr = vstart;
605 ddr_esel = find_tlb_idx((void *)ptr, 1);
606 if (ddr_esel != -1) {
607 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
608 } else {
609 printf("TLB error in function %s\n", __func__);
610 return -1;
611 }
612
613 return 0;
614 }
615
616 /*
617 * slide the testing window up to test another area
618 * for 32_bit system, the maximum testable memory is limited to
619 * CFG_MAX_MEM_MAPPED
620 */
arch_memory_test_advance(u32 * vstart,u32 * size,phys_addr_t * phys_offset)621 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
622 {
623 phys_addr_t test_cap, p_addr;
624 phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
625
626 #if !defined(CONFIG_PHYS_64BIT) || \
627 !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
628 (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
629 test_cap = p_size;
630 #else
631 test_cap = gd->ram_size;
632 #endif
633 p_addr = (*vstart) + (*size) + (*phys_offset);
634 if (p_addr < test_cap - 1) {
635 p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED);
636 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
637 return -1;
638 *vstart = CFG_SYS_DDR_SDRAM_BASE;
639 *size = (u32) p_size;
640 printf("Testing 0x%08llx - 0x%08llx\n",
641 (u64)(*vstart) + (*phys_offset),
642 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
643 } else
644 return 1;
645
646 return 0;
647 }
648
649 /* initialization for testing area */
arch_memory_test_prepare(u32 * vstart,u32 * size,phys_addr_t * phys_offset)650 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
651 {
652 phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
653
654 *vstart = CFG_SYS_DDR_SDRAM_BASE;
655 *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */
656 *phys_offset = 0;
657
658 #if !defined(CONFIG_PHYS_64BIT) || \
659 !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
660 (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
661 if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
662 puts("Cannot test more than ");
663 print_size(CFG_MAX_MEM_MAPPED,
664 " without proper 36BIT support.\n");
665 }
666 #endif
667 printf("Testing 0x%08llx - 0x%08llx\n",
668 (u64)(*vstart) + (*phys_offset),
669 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
670
671 return 0;
672 }
673
674 /* invalid TLBs for DDR and remap as normal after testing */
arch_memory_test_cleanup(u32 * vstart,u32 * size,phys_addr_t * phys_offset)675 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
676 {
677 unsigned long epn;
678 u32 tsize, valid, ptr;
679 phys_addr_t rpn = 0;
680 int ddr_esel;
681
682 /* disable the TLBs for this testing */
683 ptr = *vstart;
684
685 while (ptr < (*vstart) + (*size)) {
686 ddr_esel = find_tlb_idx((void *)ptr, 1);
687 if (ddr_esel != -1) {
688 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
689 disable_tlb(ddr_esel);
690 }
691 ptr += TSIZE_TO_BYTES(tsize);
692 }
693
694 puts("Remap DDR ");
695 setup_ddr_tlbs(gd->ram_size>>20);
696 puts("\n");
697
698 return 0;
699 }
700
arch_memory_failure_handle(void)701 void arch_memory_failure_handle(void)
702 {
703 dump_spd_ddr_reg();
704 }
705 #endif
706