1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2012 Freescale Semiconductor, Inc
4 */
5
6 #include <common.h>
7 #include <system-constants.h>
8 #include <asm-offsets.h>
9 #include <asm/global_data.h>
10 #include <asm/processor.h>
11 #include <asm/mmu.h>
12 #include <asm/fsl_law.h>
13 #include <asm/io.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #ifdef CONFIG_A003399_NOR_WORKAROUND
setup_ifc(void)18 void setup_ifc(void)
19 {
20 struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
21 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
22 phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS;
23
24 /*
25 * Adjust the TLB we were running out of to match the phys addr of the
26 * chip select we are adjusting and will return to.
27 */
28 flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024;
29
30 _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
31 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
32 MAS1_TSIZE(BOOKE_PAGESZ_4M);
33 _mas2 = FSL_BOOKE_MAS2(CONFIG_TEXT_BASE, MAS2_I | MAS2_G);
34 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
35 _mas7 = FSL_BOOKE_MAS7(flash_phys);
36
37 mtspr(MAS0, _mas0);
38 mtspr(MAS1, _mas1);
39 mtspr(MAS2, _mas2);
40 mtspr(MAS3, _mas3);
41 mtspr(MAS7, _mas7);
42
43 asm volatile("isync;msync;tlbwe;isync");
44
45 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
46 /*
47 * TLB entry for debuggging in AS1
48 * Create temporary TLB entry in AS0 to handle debug exception
49 * As on debug exception MSR is cleared i.e. Address space is changed
50 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
51 * in AS1.
52 *
53 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
54 * bacause flash's physical address is going to change as
55 * CFG_SYS_FLASH_BASE_PHYS.
56 */
57 _mas0 = MAS0_TLBSEL(1) |
58 MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
59 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
60 MAS1_TSIZE(BOOKE_PAGESZ_4M);
61 _mas2 = FSL_BOOKE_MAS2(CONFIG_TEXT_BASE, MAS2_I | MAS2_G);
62 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
63 _mas7 = FSL_BOOKE_MAS7(flash_phys);
64
65 mtspr(MAS0, _mas0);
66 mtspr(MAS1, _mas1);
67 mtspr(MAS2, _mas2);
68 mtspr(MAS3, _mas3);
69 mtspr(MAS7, _mas7);
70
71 asm volatile("isync;msync;tlbwe;isync");
72 #endif
73
74 /* Change flash's physical address */
75 ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0);
76 ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0);
77 ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0);
78
79 return;
80 }
81 #endif
82
83 /* We run cpu_init_early_f in AS = 1 */
cpu_init_early_f(void * fdt)84 void cpu_init_early_f(void *fdt)
85 {
86 u32 mas0, mas1, mas2, mas3, mas7;
87 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
88 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
89 #endif
90 #ifdef CONFIG_A003399_NOR_WORKAROUND
91 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
92 u32 *dst, *src;
93 void (*setup_ifc_sram)(void);
94 int i;
95 #endif
96
97 /* Pointer is writable since we allocated a register for it */
98 gd = (gd_t *)SYS_INIT_SP_ADDR;
99
100 /* gd area was zeroed during startup */
101
102 #ifdef CONFIG_ARCH_QEMU_E500
103 /*
104 * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
105 * so we need to populate it before it accesses it.
106 */
107 gd->fdt_blob = fdt;
108 #endif
109
110 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
111 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
112 mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G);
113 mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
114 mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS);
115
116 write_tlb(mas0, mas1, mas2, mas3, mas7);
117
118 /*
119 * Work Around for IFC Erratum A-003549. This issue is P1010
120 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
121 * Hence specifically selecting CS3.
122 */
123 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
124 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
125 #endif
126
127 #ifdef CONFIG_FSL_LAW
128 init_laws();
129 #endif
130
131 /*
132 * Work Around for IFC Erratum A003399, issue will hit only when execution
133 * from NOR Flash
134 */
135 #ifdef CONFIG_A003399_NOR_WORKAROUND
136 #define SRAM_BASE_ADDR (0x00000000)
137 /* TLB for SRAM */
138 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
139 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
140 MAS1_TSIZE(BOOKE_PAGESZ_1M);
141 mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
142 mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
143 mas7 = FSL_BOOKE_MAS7(0);
144
145 write_tlb(mas0, mas1, mas2, mas3, mas7);
146
147 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
148
149 out_be32(&l2cache->l2errdis,
150 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
151
152 out_be32(&l2cache->l2ctl,
153 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
154
155 /*
156 * Copy the code in setup_ifc to L2SRAM. Do a word copy
157 * because NOR Flash on P1010 does not support byte
158 * access (Erratum IFC-A002769)
159 */
160 setup_ifc_sram = (void *)SRAM_BASE_ADDR;
161 dst = (u32 *) SRAM_BASE_ADDR;
162 src = (u32 *) setup_ifc;
163 for (i = 0; i < 1024; i++) {
164 /* cppcheck-suppress nullPointer */
165 *dst++ = *src++;
166 }
167
168 /* cppcheck-suppress nullPointer */
169 setup_ifc_sram();
170
171 /* CLEANUP */
172 clrbits_be32(&l2cache->l2ctl,
173 (MPC85xx_L2CTL_L2E |
174 MPC85xx_L2CTL_L2SRAM_ENTIRE));
175 out_be32(&l2cache->l2srbar0, 0x0);
176 #endif
177
178 invalidate_tlb(1);
179
180 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
181 !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
182 !defined(CONFIG_NAND_SPL)
183 disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
184 #endif
185
186 init_tlbs();
187 }
188