1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 */
8
9 #include <common.h>
10 #include <clock_legacy.h>
11 #include <env.h>
12 #include <log.h>
13 #include <time.h>
14 #include <asm/global_data.h>
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
17 #include <asm/processor.h>
18 #include <linux/ctype.h>
19 #include <asm/io.h>
20 #include <asm/fsl_fdt.h>
21 #include <asm/fsl_portals.h>
22 #include <fsl_qbman.h>
23 #include <hwconfig.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
26 #endif
27 #ifdef CONFIG_SYS_DPAA_FMAN
28 #include <fsl_fman.h>
29 #endif
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 extern void ft_qe_setup(void *blob);
34 extern void ft_fixup_num_cores(void *blob);
35 extern void ft_srio_setup(void *blob);
36
37 #ifdef CONFIG_MP
38 #include "mp.h"
39
ft_fixup_cpu(void * blob,u64 memory_limit)40 void ft_fixup_cpu(void *blob, u64 memory_limit)
41 {
42 int off;
43 phys_addr_t spin_tbl_addr = get_spin_phys_addr();
44 u32 bootpg = determine_mp_bootpg(NULL);
45 u32 id = get_my_id();
46 const char *enable_method;
47 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
48 int ret;
49 int tdm_hwconfig_enabled = 0;
50 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
51 #endif
52
53 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
54 while (off != -FDT_ERR_NOTFOUND) {
55 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
56
57 if (reg) {
58 u32 phys_cpu_id = thread_to_core(*reg);
59 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
60 val = cpu_to_fdt64(val);
61 if (*reg == id) {
62 fdt_setprop_string(blob, off, "status",
63 "okay");
64 } else {
65 fdt_setprop_string(blob, off, "status",
66 "disabled");
67 }
68
69 if (hold_cores_in_reset(0)) {
70 #ifdef CONFIG_FSL_CORENET
71 /* Cores held in reset, use BRR to release */
72 enable_method = "fsl,brr-holdoff";
73 #else
74 /* Cores held in reset, use EEBPCR to release */
75 enable_method = "fsl,eebpcr-holdoff";
76 #endif
77 } else {
78 /* Cores out of reset and in a spin-loop */
79 enable_method = "spin-table";
80
81 fdt_setprop(blob, off, "cpu-release-addr",
82 &val, sizeof(val));
83 }
84
85 fdt_setprop_string(blob, off, "enable-method",
86 enable_method);
87 } else {
88 printf ("cpu NULL\n");
89 }
90 off = fdt_node_offset_by_prop_value(blob, off,
91 "device_type", "cpu", 4);
92 }
93
94 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
95 /*
96 * Extract hwconfig from environment.
97 * Search for tdm entry in hwconfig.
98 */
99 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
100 if (ret > 0)
101 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
102
103 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
104 if (tdm_hwconfig_enabled) {
105 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, SZ_16);
106 if (off < 0)
107 printf("Failed to reserve memory for tdm: %s\n",
108 fdt_strerror(off));
109 }
110 #endif
111
112 /* Reserve the boot page so OSes dont use it */
113 if ((u64)bootpg < memory_limit) {
114 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
115 if (off < 0)
116 printf("Failed to reserve memory for bootpg: %s\n",
117 fdt_strerror(off));
118 }
119
120 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
121 /*
122 * Reserve the default boot page so OSes dont use it.
123 * The default boot page is always mapped to bootpg above using
124 * boot page translation.
125 */
126 if (0xfffff000ull < memory_limit) {
127 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
128 if (off < 0) {
129 printf("Failed to reserve memory for 0xfffff000: %s\n",
130 fdt_strerror(off));
131 }
132 }
133 #endif
134
135 /* Reserve spin table page */
136 if (spin_tbl_addr < memory_limit) {
137 off = fdt_add_mem_rsv(blob,
138 (spin_tbl_addr & ~0xffful), 4096);
139 if (off < 0)
140 printf("Failed to reserve memory for spin table: %s\n",
141 fdt_strerror(off));
142 }
143 #ifdef CONFIG_DEEP_SLEEP
144 #ifdef CONFIG_SPL_MMC_BOOT
145 off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START,
146 CFG_SYS_MMC_U_BOOT_SIZE);
147 if (off < 0)
148 printf("Failed to reserve memory for SD deep sleep: %s\n",
149 fdt_strerror(off));
150 #elif defined(CONFIG_SPL_SPI_BOOT)
151 off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START,
152 CFG_SYS_SPI_FLASH_U_BOOT_SIZE);
153 if (off < 0)
154 printf("Failed to reserve memory for SPI deep sleep: %s\n",
155 fdt_strerror(off));
156 #endif
157 #endif
158 }
159 #endif
160
161 #ifdef CONFIG_SYS_FSL_CPC
ft_fixup_l3cache(void * blob,int off)162 static inline void ft_fixup_l3cache(void *blob, int off)
163 {
164 u32 line_size, num_ways, size, num_sets;
165 cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
166 u32 cfg0 = in_be32(&cpc->cpccfg0);
167
168 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC;
169 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
170 line_size = CPC_CFG0_LINE_SZ(cfg0);
171 num_sets = size / (line_size * num_ways);
172
173 fdt_setprop(blob, off, "cache-unified", NULL, 0);
174 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
175 fdt_setprop_cell(blob, off, "cache-size", size);
176 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
177 fdt_setprop_cell(blob, off, "cache-level", 3);
178 #ifdef CONFIG_SYS_CACHE_STASHING
179 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
180 #endif
181 }
182 #else
183 #define ft_fixup_l3cache(x, y)
184 #endif
185
186 #if defined(CONFIG_L2_CACHE) || \
187 defined(CONFIG_BACKSIDE_L2_CACHE) || \
188 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
ft_fixup_l2cache_compatible(void * blob,int off)189 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
190 {
191 int len;
192 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
193
194 if (cpu) {
195 char buf[40];
196
197 if (isdigit(cpu->name[0])) {
198 /* MPCxxxx, where xxxx == 4-digit number */
199 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
200 cpu->name) + 1;
201 } else {
202 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
203 len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
204 tolower(cpu->name[0]), cpu->name + 1) + 1;
205 }
206
207 /*
208 * append "cache" after the NULL character that the previous
209 * sprintf wrote. This is how a device tree stores multiple
210 * strings in a property.
211 */
212 len += sprintf(buf + len, "cache") + 1;
213
214 fdt_setprop(blob, off, "compatible", buf, len);
215 }
216 }
217 #endif
218
219 #if defined(CONFIG_L2_CACHE)
220 /* return size in kilobytes */
l2cache_size(void)221 static inline u32 l2cache_size(void)
222 {
223 volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
224 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
225 u32 ver = SVR_SOC_VER(get_svr());
226
227 switch (l2siz_field) {
228 case 0x0:
229 break;
230 case 0x1:
231 if (ver == SVR_8540 || ver == SVR_8560 ||
232 ver == SVR_8541 || ver == SVR_8555)
233 return 128;
234 else
235 return 256;
236 break;
237 case 0x2:
238 if (ver == SVR_8540 || ver == SVR_8560 ||
239 ver == SVR_8541 || ver == SVR_8555)
240 return 256;
241 else
242 return 512;
243 break;
244 case 0x3:
245 return 1024;
246 break;
247 }
248
249 return 0;
250 }
251
ft_fixup_l2cache(void * blob)252 static inline void ft_fixup_l2cache(void *blob)
253 {
254 int off;
255 u32 *ph;
256
257 const u32 line_size = 32;
258 const u32 num_ways = 8;
259 const u32 size = l2cache_size() * 1024;
260 const u32 num_sets = size / (line_size * num_ways);
261
262 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
263 if (off < 0) {
264 debug("no cpu node fount\n");
265 return;
266 }
267
268 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
269
270 if (ph == NULL) {
271 debug("no next-level-cache property\n");
272 return;
273 }
274
275 off = fdt_node_offset_by_phandle(blob, *ph);
276 if (off < 0) {
277 printf("%s: %s\n", __func__, fdt_strerror(off));
278 return;
279 }
280
281 ft_fixup_l2cache_compatible(blob, off);
282 fdt_setprop(blob, off, "cache-unified", NULL, 0);
283 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
284 fdt_setprop_cell(blob, off, "cache-size", size);
285 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
286 fdt_setprop_cell(blob, off, "cache-level", 2);
287
288 /* we dont bother w/L3 since no platform of this type has one */
289 }
290 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
291 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
ft_fixup_l2cache(void * blob)292 static inline void ft_fixup_l2cache(void *blob)
293 {
294 int off, l2_off, l3_off = -1;
295 u32 *ph;
296 #ifdef CONFIG_BACKSIDE_L2_CACHE
297 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
298 #else
299 struct ccsr_cluster_l2 *l2cache =
300 (struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
301 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
302 #endif
303 u32 size, line_size, num_ways, num_sets;
304 int has_l2 = 1;
305
306 /* P2040/P2040E has no L2, so dont set any L2 props */
307 if (SVR_SOC_VER(get_svr()) == SVR_P2040)
308 has_l2 = 0;
309
310 size = (l2cfg0 & 0x3fff) * 64 * 1024;
311 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
312 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
313 num_sets = size / (line_size * num_ways);
314
315 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
316
317 while (off != -FDT_ERR_NOTFOUND) {
318 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
319
320 if (ph == NULL) {
321 debug("no next-level-cache property\n");
322 goto next;
323 }
324
325 l2_off = fdt_node_offset_by_phandle(blob, *ph);
326 if (l2_off < 0) {
327 printf("%s: %s\n", __func__, fdt_strerror(off));
328 goto next;
329 }
330
331 if (has_l2) {
332 #ifdef CONFIG_SYS_CACHE_STASHING
333 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
334 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
335 /* Only initialize every eighth thread */
336 if (reg && !((*reg) % 8)) {
337 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
338 (*reg / 4) + 32 + 1);
339 }
340 #else
341 if (reg) {
342 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
343 (*reg * 2) + 32 + 1);
344 }
345 #endif
346 #endif
347
348 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
349 fdt_setprop_cell(blob, l2_off, "cache-block-size",
350 line_size);
351 fdt_setprop_cell(blob, l2_off, "cache-size", size);
352 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
353 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
354 ft_fixup_l2cache_compatible(blob, l2_off);
355 }
356
357 if (l3_off < 0) {
358 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
359
360 if (ph == NULL) {
361 debug("no next-level-cache property\n");
362 goto next;
363 }
364 l3_off = *ph;
365 }
366 next:
367 off = fdt_node_offset_by_prop_value(blob, off,
368 "device_type", "cpu", 4);
369 }
370 if (l3_off > 0) {
371 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
372 if (l3_off < 0) {
373 printf("%s: %s\n", __func__, fdt_strerror(off));
374 return;
375 }
376 ft_fixup_l3cache(blob, l3_off);
377 }
378 }
379 #else
380 #define ft_fixup_l2cache(x)
381 #endif
382
ft_fixup_cache(void * blob)383 static inline void ft_fixup_cache(void *blob)
384 {
385 int off;
386
387 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
388
389 while (off != -FDT_ERR_NOTFOUND) {
390 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
391 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
392 u32 isize, iline_size, inum_sets, inum_ways;
393 u32 dsize, dline_size, dnum_sets, dnum_ways;
394
395 /* d-side config */
396 dsize = (l1cfg0 & 0x7ff) * 1024;
397 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
398 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
399 dnum_sets = dsize / (dline_size * dnum_ways);
400
401 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
402 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
403 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
404
405 #ifdef CONFIG_SYS_CACHE_STASHING
406 {
407 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
408 if (reg)
409 fdt_setprop_cell(blob, off, "cache-stash-id",
410 (*reg * 2) + 32 + 0);
411 }
412 #endif
413
414 /* i-side config */
415 isize = (l1cfg1 & 0x7ff) * 1024;
416 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
417 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
418 inum_sets = isize / (iline_size * inum_ways);
419
420 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
421 fdt_setprop_cell(blob, off, "i-cache-size", isize);
422 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
423
424 off = fdt_node_offset_by_prop_value(blob, off,
425 "device_type", "cpu", 4);
426 }
427
428 ft_fixup_l2cache(blob);
429 }
430
431
fdt_add_enet_stashing(void * fdt)432 void fdt_add_enet_stashing(void *fdt)
433 {
434 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
435
436 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
437
438 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
439 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
440 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
441 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
442 }
443
444 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
445 #ifdef CONFIG_SYS_DPAA_FMAN
ft_fixup_clks(void * blob,const char * compat,u32 offset,unsigned long freq)446 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
447 unsigned long freq)
448 {
449 phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS;
450 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
451
452 if (off >= 0) {
453 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
454 if (off > 0)
455 printf("WARNING enable to set clock-frequency "
456 "for %s: %s\n", compat, fdt_strerror(off));
457 }
458 }
459 #endif
460
ft_fixup_dpaa_clks(void * blob)461 static void ft_fixup_dpaa_clks(void *blob)
462 {
463 sys_info_t sysinfo;
464
465 get_sys_info(&sysinfo);
466 #ifdef CONFIG_SYS_DPAA_FMAN
467 ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
468 sysinfo.freq_fman[0]);
469
470 #if (CFG_SYS_NUM_FMAN == 2)
471 ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
472 sysinfo.freq_fman[1]);
473 #endif
474 #endif
475
476 #ifdef CONFIG_SYS_DPAA_QBMAN
477 do_fixup_by_compat_u32(blob, "fsl,qman",
478 "clock-frequency", sysinfo.freq_qman, 1);
479 #endif
480
481 #ifdef CONFIG_SYS_DPAA_PME
482 do_fixup_by_compat_u32(blob, "fsl,pme",
483 "clock-frequency", sysinfo.freq_pme, 1);
484 #endif
485 }
486 #else
487 #define ft_fixup_dpaa_clks(x)
488 #endif
489
490 #ifdef CONFIG_QE
ft_fixup_qe_snum(void * blob)491 static void ft_fixup_qe_snum(void *blob)
492 {
493 unsigned int svr;
494
495 svr = mfspr(SPRN_SVR);
496 if (SVR_SOC_VER(svr) == SVR_8569) {
497 if(IS_SVR_REV(svr, 1, 0))
498 do_fixup_by_compat_u32(blob, "fsl,qe",
499 "fsl,qe-num-snums", 46, 1);
500 else
501 do_fixup_by_compat_u32(blob, "fsl,qe",
502 "fsl,qe-num-snums", 76, 1);
503 }
504 }
505 #endif
506
507 #if defined(CONFIG_ARCH_P4080)
fdt_fixup_usb(void * fdt)508 static void fdt_fixup_usb(void *fdt)
509 {
510 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
511 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
512 int off;
513
514 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
515 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
516 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
517 fdt_status_disabled(fdt, off);
518
519 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
520 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
521 FSL_CORENET_RCWSR11_EC2_USB2)
522 fdt_status_disabled(fdt, off);
523 }
524 #else
525 #define fdt_fixup_usb(x)
526 #endif
527
528 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
fdt_fixup_dma3(void * blob)529 void fdt_fixup_dma3(void *blob)
530 {
531 /* the 3rd DMA is not functional if SRIO2 is chosen */
532 int nodeoff;
533 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
534
535 #define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
536 #if defined(CONFIG_ARCH_T2080)
537 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
538 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
539 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
540
541 switch (srds_prtcl_s2) {
542 case 0x29:
543 case 0x2d:
544 case 0x2e:
545 #elif defined(CONFIG_ARCH_T4240)
546 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
547 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
548 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
549
550 switch (srds_prtcl_s4) {
551 case 6:
552 case 8:
553 case 14:
554 case 16:
555 #endif
556 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
557 CFG_SYS_ELO3_DMA3);
558 if (nodeoff > 0)
559 fdt_status_disabled(blob, nodeoff);
560 else
561 printf("WARNING: unable to disable dma3\n");
562 break;
563 default:
564 break;
565 }
566 }
567 #else
568 #define fdt_fixup_dma3(x)
569 #endif
570
571 #if defined(CONFIG_ARCH_T1040)
572 static void fdt_fixup_l2_switch(void *blob)
573 {
574 uchar l2swaddr[6];
575 int node;
576
577 /* The l2switch node from device-tree has
578 * compatible string "vitesse-9953" */
579 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
580 if (node == -FDT_ERR_NOTFOUND)
581 /* no l2switch node has been found */
582 return;
583
584 /* Get MAC address for the l2switch from "l2switchaddr"*/
585 if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
586 printf("Warning: MAC address for l2switch not found\n");
587 memset(l2swaddr, 0, sizeof(l2swaddr));
588 }
589
590 /* Add MAC address to l2switch node */
591 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
592 sizeof(l2swaddr));
593 }
594 #else
595 #define fdt_fixup_l2_switch(x)
596 #endif
597
598 void ft_cpu_setup(void *blob, struct bd_info *bd)
599 {
600 int off;
601 int val;
602 int len;
603 sys_info_t sysinfo;
604
605 /* delete crypto node if not on an E-processor */
606 if (!IS_E_PROCESSOR(get_svr()))
607 fdt_fixup_crypto_node(blob, 0);
608 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
609 else {
610 ccsr_sec_t __iomem *sec;
611
612 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
613 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
614 }
615 #endif
616
617 fdt_add_enet_stashing(blob);
618
619 #ifndef CFG_FSL_TBCLK_EXTRA_DIV
620 #define CFG_FSL_TBCLK_EXTRA_DIV 1
621 #endif
622 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
623 "timebase-frequency", get_tbclk() / CFG_FSL_TBCLK_EXTRA_DIV,
624 1);
625 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
626 "bus-frequency", bd->bi_busfreq, 1);
627 get_sys_info(&sysinfo);
628 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
629 while (off != -FDT_ERR_NOTFOUND) {
630 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
631 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
632 fdt_setprop(blob, off, "clock-frequency", &val, 4);
633 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
634 "cpu", 4);
635 }
636 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
637 "bus-frequency", bd->bi_busfreq, 1);
638
639 #ifdef CONFIG_QE
640 ft_qe_setup(blob);
641 ft_fixup_qe_snum(blob);
642 #endif
643
644 #ifdef CONFIG_SYS_DPAA_FMAN
645 fdt_fixup_fman_firmware(blob);
646 #endif
647
648 #ifdef CONFIG_SYS_NS16550
649 do_fixup_by_compat_u32(blob, "ns16550",
650 "clock-frequency", CFG_SYS_NS16550_CLK, 1);
651 #endif
652
653 #ifdef CONFIG_FSL_CORENET
654 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
655 "clock-frequency", get_board_sys_clk(), 1);
656 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
657 "clock-frequency", get_board_sys_clk(), 1);
658 do_fixup_by_compat_u32(blob, "fsl,mpic",
659 "clock-frequency", get_bus_freq(0)/2, 1);
660 #else
661 do_fixup_by_compat_u32(blob, "fsl,mpic",
662 "clock-frequency", get_bus_freq(0), 1);
663 #endif
664
665 fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
666
667 #ifdef CONFIG_MP
668 ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
669 ft_fixup_num_cores(blob);
670 #endif
671
672 ft_fixup_cache(blob);
673
674 #if defined(CONFIG_FSL_ESDHC)
675 fdt_fixup_esdhc(blob, bd);
676 #endif
677
678 ft_fixup_dpaa_clks(blob);
679
680 #if defined(CFG_SYS_BMAN_MEM_PHYS)
681 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
682 (u64)CFG_SYS_BMAN_MEM_PHYS,
683 CFG_SYS_BMAN_MEM_SIZE);
684 fdt_fixup_bportals(blob);
685 #endif
686
687 #if defined(CFG_SYS_QMAN_MEM_PHYS)
688 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
689 (u64)CFG_SYS_QMAN_MEM_PHYS,
690 CFG_SYS_QMAN_MEM_SIZE);
691
692 fdt_fixup_qportals(blob);
693 #endif
694
695 #ifdef CONFIG_SYS_SRIO
696 ft_srio_setup(blob);
697 #endif
698
699 /*
700 * system-clock = CCB clock/2
701 * Here gd->bus_clk = CCB clock
702 * We are using the system clock as 1588 Timer reference
703 * clock source select
704 */
705 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
706 "timer-frequency", gd->bus_clk/2, 1);
707
708 /*
709 * clock-freq should change to clock-frequency and
710 * flexcan-v1.0 should change to p1010-flexcan respectively
711 * in the future.
712 */
713 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
714 "clock_freq", gd->bus_clk/2, 1);
715
716 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
717 "clock-frequency", gd->bus_clk/2, 1);
718
719 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
720 "clock-frequency", gd->bus_clk/2, 1);
721
722 fdt_fixup_usb(blob);
723
724 fdt_fixup_l2_switch(blob);
725
726 fdt_fixup_dma3(blob);
727 }
728
729 /*
730 * For some CCSR devices, we only have the virtual address, not the physical
731 * address. This is because we map CCSR as a whole, so we typically don't need
732 * a macro for the physical address of any device within CCSR. In this case,
733 * we calculate the physical address of that device using it's the difference
734 * between the virtual address of the device and the virtual address of the
735 * beginning of CCSR.
736 */
737 #define CCSR_VIRT_TO_PHYS(x) \
738 (CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR))
739
740 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
741 {
742 printf("Warning: U-Boot configured %s at address %llx,\n"
743 "but the device tree has it at %llx\n", name, uaddr, daddr);
744 }
745
746 /*
747 * Verify the device tree
748 *
749 * This function compares several CONFIG_xxx macros that contain physical
750 * addresses with the corresponding nodes in the device tree, to see if
751 * the physical addresses are all correct. For example, if
752 * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address
753 * of the first UART. We convert this to a physical address and compare
754 * that with the physical address of the first ns16550-compatible node
755 * in the device tree. If they don't match, then we display a warning.
756 *
757 * Returns 1 on success, 0 on failure
758 */
759 int ft_verify_fdt(void *fdt)
760 {
761 uint64_t addr = 0;
762 int aliases;
763 int off;
764
765 /* First check the CCSR base address */
766 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
767 if (off > 0) {
768 int size;
769 u32 naddr;
770 const fdt32_t *prop;
771
772 naddr = fdt_address_cells(fdt, off);
773 prop = fdt_getprop(fdt, off, "ranges", &size);
774 addr = fdt_translate_address(fdt, off, prop + naddr);
775 }
776
777 if (!addr) {
778 printf("Warning: could not determine base CCSR address in "
779 "device tree\n");
780 /* No point in checking anything else */
781 return 0;
782 }
783
784 if (addr != CFG_SYS_CCSRBAR_PHYS) {
785 msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr);
786 /* No point in checking anything else */
787 return 0;
788 }
789
790 /*
791 * Check some nodes via aliases. We assume that U-Boot and the device
792 * tree enumerate the devices equally. E.g. the first serial port in
793 * U-Boot is the same as "serial0" in the device tree.
794 */
795 aliases = fdt_path_offset(fdt, "/aliases");
796 if (aliases > 0) {
797 #ifdef CFG_SYS_NS16550_COM1
798 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
799 CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1)))
800 return 0;
801 #endif
802
803 #ifdef CFG_SYS_NS16550_COM2
804 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
805 CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2)))
806 return 0;
807 #endif
808 }
809
810 /*
811 * The localbus node is typically a root node, even though the lbc
812 * controller is part of CCSR. If we were to put the lbc node under
813 * the SOC node, then the 'ranges' property in the lbc node would
814 * translate through the 'ranges' property of the parent SOC node, and
815 * we don't want that. Since it's a separate node, it's possible for
816 * the 'reg' property to be wrong, so check it here. For now, we
817 * only check for "fsl,elbc" nodes.
818 */
819 #ifdef CFG_SYS_LBC_ADDR
820 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
821 if (off > 0) {
822 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
823 if (reg) {
824 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR);
825
826 addr = fdt_translate_address(fdt, off, reg);
827 if (uaddr != addr) {
828 msg("the localbus", uaddr, addr);
829 return 0;
830 }
831 }
832 }
833 #endif
834
835 return 1;
836 }
837
838 void fdt_del_diu(void *blob)
839 {
840 int nodeoff = 0;
841
842 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
843 "fsl,diu")) >= 0) {
844 fdt_del_node(blob, nodeoff);
845 }
846 }
847