1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __FSL_SECURE_BOOT_H 7 #define __FSL_SECURE_BOOT_H 8 #include <asm/config_mpc85xx.h> 9 10 #ifdef CONFIG_NXP_ESBC 11 #if defined(CONFIG_FSL_CORENET) 12 #define CFG_SYS_PBI_FLASH_BASE 0xc0000000 13 #else 14 #define CFG_SYS_PBI_FLASH_BASE 0xce000000 15 #endif 16 #define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000 17 18 #if defined(CONFIG_TARGET_T2080QDS) || \ 19 defined(CONFIG_TARGET_T2080RDB) || \ 20 defined(CONFIG_TARGET_T1042D4RDB) || \ 21 defined(CONFIG_ARCH_T1024) 22 #undef CFG_SYS_INIT_L3_ADDR 23 #define CFG_SYS_INIT_L3_ADDR 0xbff00000 24 #endif 25 26 #if defined(CONFIG_RAMBOOT_PBL) 27 #undef CFG_SYS_INIT_L3_ADDR 28 #ifdef CFG_SYS_INIT_L3_VADDR 29 #define CFG_SYS_INIT_L3_ADDR \ 30 (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 31 0xbff00000 32 #else 33 #define CFG_SYS_INIT_L3_ADDR 0xbff00000 34 #endif 35 #endif 36 #endif /* #ifdef CONFIG_NXP_ESBC */ 37 38 #ifdef CONFIG_CHAIN_OF_TRUST 39 #ifdef CONFIG_SPL_BUILD 40 /* 41 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init 42 * due to space crunch on CPC and thus malloc will not work. 43 */ 44 #define CFG_SPL_PPAACT_ADDR 0x2e000000 45 #define CFG_SPL_SPAACT_ADDR 0x2f000000 46 #define CFG_SPL_JR0_LIODN_S 454 47 #define CFG_SPL_JR0_LIODN_NS 458 48 #endif /* ifdef CONFIG_SPL_BUILD */ 49 50 #ifndef CONFIG_SPL_BUILD 51 #include <config_fsl_chain_trust.h> 52 #endif /* #ifndef CONFIG_SPL_BUILD */ 53 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 54 #endif 55