1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <cpu.h>
8 #include <dm.h>
9 #include <dm/lists.h>
10 #include <event.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/encoding.h>
14 #include <asm/system.h>
15 #include <dm/uclass-internal.h>
16 #include <linux/bitops.h>
17
18 /*
19 * The variables here must be stored in the data section since they are used
20 * before the bss section is available.
21 */
22 #if !CONFIG_IS_ENABLED(XIP)
23 u32 hart_lottery __section(".data") = 0;
24
25 #ifdef CONFIG_AVAILABLE_HARTS
26 /*
27 * The main hart running U-Boot has acquired available_harts_lock until it has
28 * finished initialization of global data.
29 */
30 u32 available_harts_lock = 1;
31 #endif
32 #endif
33
supports_extension(char ext)34 static inline bool supports_extension(char ext)
35 {
36 #if CONFIG_IS_ENABLED(RISCV_MMODE)
37 return csr_read(CSR_MISA) & (1 << (ext - 'a'));
38 #elif CONFIG_CPU
39 struct udevice *dev;
40 char desc[32];
41 int i;
42
43 uclass_find_first_device(UCLASS_CPU, &dev);
44 if (!dev) {
45 debug("unable to find the RISC-V cpu device\n");
46 return false;
47 }
48 if (!cpu_get_desc(dev, desc, sizeof(desc))) {
49 /*
50 * skip the first 4 characters (rv32|rv64) and
51 * check until underscore
52 */
53 for (i = 4; i < sizeof(desc); i++) {
54 if (desc[i] == '_' || desc[i] == '\0')
55 break;
56 if (desc[i] == ext)
57 return true;
58 }
59 }
60
61 return false;
62 #else /* !CONFIG_CPU */
63 #warning "There is no way to determine the available extensions in S-mode."
64 #warning "Please convert your board to use the RISC-V CPU driver."
65 return false;
66 #endif /* CONFIG_CPU */
67 }
68
riscv_cpu_probe(void)69 static int riscv_cpu_probe(void)
70 {
71 #ifdef CONFIG_CPU
72 int ret;
73
74 /* probe cpus so that RISC-V timer can be bound */
75 ret = cpu_probe_all();
76 if (ret)
77 return log_msg_ret("RISC-V cpus probe failed\n", ret);
78 #endif
79
80 return 0;
81 }
82
83 /*
84 * This is called on secondary harts just after the IPI is init'd. Currently
85 * there's nothing to do, since we just need to clear any existing IPIs, and
86 * that is handled by the sending of an ipi itself.
87 */
88 #if CONFIG_IS_ENABLED(SMP)
dummy_pending_ipi_clear(ulong hart,ulong arg0,ulong arg1)89 static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
90 {
91 }
92 #endif
93
riscv_cpu_setup(void * ctx,struct event * event)94 int riscv_cpu_setup(void *ctx, struct event *event)
95 {
96 int ret;
97
98 ret = riscv_cpu_probe();
99 if (ret)
100 return ret;
101
102 /* Enable FPU */
103 if (supports_extension('d') || supports_extension('f')) {
104 csr_set(MODE_PREFIX(status), MSTATUS_FS);
105 csr_write(CSR_FCSR, 0);
106 }
107
108 if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
109 /*
110 * Enable perf counters for cycle, time,
111 * and instret counters only
112 */
113 if (supports_extension('u')) {
114 #ifdef CONFIG_RISCV_PRIV_1_9
115 csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
116 csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
117 #else
118 csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
119 #endif
120 }
121
122 /* Disable paging */
123 if (supports_extension('s'))
124 #ifdef CONFIG_RISCV_PRIV_1_9
125 csr_read_clear(CSR_MSTATUS, SR_VM);
126 #else
127 csr_write(CSR_SATP, 0);
128 #endif
129 }
130
131 #if CONFIG_IS_ENABLED(SMP)
132 ret = riscv_init_ipi();
133 if (ret)
134 return ret;
135
136 /*
137 * Clear all pending IPIs on secondary harts. We don't do anything on
138 * the boot hart, since we never send an IPI to ourselves, and no
139 * interrupts are enabled
140 */
141 ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
142 if (ret)
143 return ret;
144 #endif
145
146 return 0;
147 }
148 EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
149
arch_early_init_r(void)150 int arch_early_init_r(void)
151 {
152 int ret;
153
154 ret = riscv_cpu_probe();
155 if (ret)
156 return ret;
157
158 if (IS_ENABLED(CONFIG_SYSRESET_SBI))
159 device_bind_driver(gd->dm_root, "sbi-sysreset",
160 "sbi-sysreset", NULL);
161
162 return 0;
163 }
164
165 /**
166 * harts_early_init() - A callback function called by start.S to configure
167 * feature settings of each hart.
168 *
169 * In a multi-core system, memory access shall be careful here, it shall
170 * take care of race conditions.
171 */
harts_early_init(void)172 __weak void harts_early_init(void)
173 {
174 }
175