1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021-2022 Microchip Technology Inc.
4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
6
7/dts-v1/;
8
9#include "microchip-mpfs.dtsi"
10
11/* Clock frequency (in Hz) of the rtcclk */
12#define RTCCLK_FREQ		1000000
13
14/ {
15	model = "Microchip PolarFire-SoC Icicle Kit";
16	compatible = "microchip,mpfs-icicle-reference-rtlv2210",
17		     "microchip,mpfs-icicle-kit", "microchip,mpfs";
18
19	aliases {
20		serial1 = &uart1;
21		ethernet0 = &mac1;
22		spi0 = &qspi;
23	};
24
25	chosen {
26		stdout-path = "serial1";
27	};
28
29	cpus {
30		timebase-frequency = <RTCCLK_FREQ>;
31	};
32
33	ddrc_cache_lo: memory@80000000 {
34		device_type = "memory";
35		reg = <0x0 0x80000000 0x0 0x40000000>;
36		status = "okay";
37	};
38
39	ddrc_cache_hi: memory@1040000000 {
40		device_type = "memory";
41		reg = <0x10 0x40000000 0x0 0x40000000>;
42		status = "okay";
43	};
44
45	reserved-memory {
46		#address-cells = <2>;
47		#size-cells = <2>;
48		ranges;
49
50		hss_payload: region@BFC00000 {
51			reg = <0x0 0xBFC00000 0x0 0x400000>;
52			no-map;
53		};
54	};
55};
56
57&refclk {
58	clock-frequency = <125000000>;
59};
60
61&uart1 {
62	status = "okay";
63};
64
65&mmc {
66	status = "okay";
67
68	bus-width = <4>;
69	disable-wp;
70	cap-mmc-highspeed;
71	cap-sd-highspeed;
72	card-detect-delay = <200>;
73	mmc-ddr-1_8v;
74	mmc-hs200-1_8v;
75	sd-uhs-sdr12;
76	sd-uhs-sdr25;
77	sd-uhs-sdr50;
78	sd-uhs-sdr104;
79};
80
81&i2c1 {
82	status = "okay";
83	clock-frequency = <100000>;
84
85	pac193x: pac193x@10 {
86		compatible = "microchip,pac1934";
87		reg = <0x10>;
88		samp-rate = <64>;
89		status = "okay";
90		ch1: channel0 {
91			uohms-shunt-res = <10000>;
92			rail-name = "VDDREG";
93			channel_enabled;
94		};
95		ch2: channel1 {
96			uohms-shunt-res = <10000>;
97			rail-name = "VDDA25";
98			channel_enabled;
99		};
100		ch3: channel2 {
101			uohms-shunt-res = <10000>;
102			rail-name = "VDD25";
103			channel_enabled;
104		};
105		ch4: channel3 {
106			uohms-shunt-res = <10000>;
107			rail-name = "VDDA_REG";
108			channel_enabled;
109		};
110	};
111};
112
113&mac1 {
114	status = "okay";
115	phy-mode = "sgmii";
116	phy-handle = <&phy1>;
117	phy1: ethernet-phy@9 {
118		reg = <9>;
119		ti,fifo-depth = <0x1>;
120	};
121};
122
123&qspi {
124	status = "okay";
125	num-cs = <1>;
126
127	flash0: flash@0 {
128		compatible = "spi-nand";
129		reg = <0x0>;
130		spi-tx-bus-width = <4>;
131		spi-rx-bus-width = <4>;
132		spi-max-frequency = <20000000>;
133		spi-cpol;
134		spi-cpha;
135	};
136};
137