1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * 5 * Author: Yanhong Wang <yanhong.wang@starfivetech.com> 6 */ 7 8 #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ 9 #define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ 10 11 /* SYSCRG resets */ 12 #define JH7110_SYSRST_JTAG2APB 0 13 #define JH7110_SYSRST_SYSCON 1 14 #define JH7110_SYSRST_IOMUX_APB 2 15 #define JH7110_SYSRST_BUS 3 16 #define JH7110_SYSRST_DEBUG 4 17 #define JH7110_SYSRST_CORE0 5 18 #define JH7110_SYSRST_CORE1 6 19 #define JH7110_SYSRST_CORE2 7 20 #define JH7110_SYSRST_CORE3 8 21 #define JH7110_SYSRST_CORE4 9 22 #define JH7110_SYSRST_CORE0_ST 10 23 #define JH7110_SYSRST_CORE1_ST 11 24 #define JH7110_SYSRST_CORE2_ST 12 25 #define JH7110_SYSRST_CORE3_ST 13 26 #define JH7110_SYSRST_CORE4_ST 14 27 #define JH7110_SYSRST_TRACE0 15 28 #define JH7110_SYSRST_TRACE1 16 29 #define JH7110_SYSRST_TRACE2 17 30 #define JH7110_SYSRST_TRACE3 18 31 #define JH7110_SYSRST_TRACE4 19 32 #define JH7110_SYSRST_TRACE_COM 20 33 #define JH7110_SYSRST_GPU_APB 21 34 #define JH7110_SYSRST_GPU_DOMA 22 35 #define JH7110_SYSRST_NOC_BUS_APB_BUS 23 36 #define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 37 #define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 38 #define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 39 #define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 40 #define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 41 #define JH7110_SYSRST_NOC_BUS_DDRC 29 42 #define JH7110_SYSRST_NOC_BUS_STG_AXI 30 43 #define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 44 45 #define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 46 #define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 47 #define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 48 #define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 49 #define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 50 #define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 51 #define JH7110_SYSRST_DDR_AXI 38 52 #define JH7110_SYSRST_DDR_OSC 39 53 #define JH7110_SYSRST_DDR_APB 40 54 #define JH7110_SYSRST_DOM_ISP_TOP_N 41 55 #define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 56 #define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 57 #define JH7110_SYSRST_CODAJ12_AXI 44 58 #define JH7110_SYSRST_CODAJ12_CORE 45 59 #define JH7110_SYSRST_CODAJ12_APB 46 60 #define JH7110_SYSRST_WAVE511_AXI 47 61 #define JH7110_SYSRST_WAVE511_BPU 48 62 #define JH7110_SYSRST_WAVE511_VCE 49 63 #define JH7110_SYSRST_WAVE511_APB 50 64 #define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 65 #define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 66 #define JH7110_SYSRST_AXIMEM0_AXI 53 67 #define JH7110_SYSRST_WAVE420L_AXI 54 68 #define JH7110_SYSRST_WAVE420L_BPU 55 69 #define JH7110_SYSRST_WAVE420L_VCE 56 70 #define JH7110_SYSRST_WAVE420L_APB 57 71 #define JH7110_SYSRST_AXIMEM1_AXI 58 72 #define JH7110_SYSRST_AXIMEM2_AXI 59 73 #define JH7110_SYSRST_INTMEM 60 74 #define JH7110_SYSRST_QSPI_AHB 61 75 #define JH7110_SYSRST_QSPI_APB 62 76 #define JH7110_SYSRST_QSPI_REF 63 77 78 #define JH7110_SYSRST_SDIO0_AHB 64 79 #define JH7110_SYSRST_SDIO1_AHB 65 80 #define JH7110_SYSRST_GMAC1_AXI 66 81 #define JH7110_SYSRST_GMAC1_AHB 67 82 #define JH7110_SYSRST_MAILBOX 68 83 #define JH7110_SYSRST_SPI0_APB 69 84 #define JH7110_SYSRST_SPI1_APB 70 85 #define JH7110_SYSRST_SPI2_APB 71 86 #define JH7110_SYSRST_SPI3_APB 72 87 #define JH7110_SYSRST_SPI4_APB 73 88 #define JH7110_SYSRST_SPI5_APB 74 89 #define JH7110_SYSRST_SPI6_APB 75 90 #define JH7110_SYSRST_I2C0_APB 76 91 #define JH7110_SYSRST_I2C1_APB 77 92 #define JH7110_SYSRST_I2C2_APB 78 93 #define JH7110_SYSRST_I2C3_APB 79 94 #define JH7110_SYSRST_I2C4_APB 80 95 #define JH7110_SYSRST_I2C5_APB 81 96 #define JH7110_SYSRST_I2C6_APB 82 97 #define JH7110_SYSRST_UART0_APB 83 98 #define JH7110_SYSRST_UART0_CORE 84 99 #define JH7110_SYSRST_UART1_APB 85 100 #define JH7110_SYSRST_UART1_CORE 86 101 #define JH7110_SYSRST_UART2_APB 87 102 #define JH7110_SYSRST_UART2_CORE 88 103 #define JH7110_SYSRST_UART3_APB 89 104 #define JH7110_SYSRST_UART3_CORE 90 105 #define JH7110_SYSRST_UART4_APB 91 106 #define JH7110_SYSRST_UART4_CORE 92 107 #define JH7110_SYSRST_UART5_APB 93 108 #define JH7110_SYSRST_UART5_CORE 94 109 #define JH7110_SYSRST_SPDIF_APB 95 110 111 #define JH7110_SYSRST_PWMDAC_APB 96 112 #define JH7110_SYSRST_PDM_DMIC 97 113 #define JH7110_SYSRST_PDM_APB 98 114 #define JH7110_SYSRST_I2SRX_APB 99 115 #define JH7110_SYSRST_I2SRX_BCLK 100 116 #define JH7110_SYSRST_I2STX0_APB 101 117 #define JH7110_SYSRST_I2STX0_BCLK 102 118 #define JH7110_SYSRST_I2STX1_APB 103 119 #define JH7110_SYSRST_I2STX1_BCLK 104 120 #define JH7110_SYSRST_TDM_AHB 105 121 #define JH7110_SYSRST_TDM_CORE 106 122 #define JH7110_SYSRST_TDM_APB 107 123 #define JH7110_SYSRST_PWM_APB 108 124 #define JH7110_SYSRST_WDT_APB 109 125 #define JH7110_SYSRST_WDT_CORE 110 126 #define JH7110_SYSRST_CAN0_APB 111 127 #define JH7110_SYSRST_CAN0_CORE 112 128 #define JH7110_SYSRST_CAN0_TIMER 113 129 #define JH7110_SYSRST_CAN1_APB 114 130 #define JH7110_SYSRST_CAN1_CORE 115 131 #define JH7110_SYSRST_CAN1_TIMER 116 132 #define JH7110_SYSRST_TIMER_APB 117 133 #define JH7110_SYSRST_TIMER0 118 134 #define JH7110_SYSRST_TIMER1 119 135 #define JH7110_SYSRST_TIMER2 120 136 #define JH7110_SYSRST_TIMER3 121 137 #define JH7110_SYSRST_INT_CTRL_APB 122 138 #define JH7110_SYSRST_TEMP_APB 123 139 #define JH7110_SYSRST_TEMP_CORE 124 140 #define JH7110_SYSRST_JTAG_CERTIFICATION 125 141 142 #define JH7110_SYSRST_END 126 143 144 /* AONCRG resets */ 145 #define JH7110_AONRST_GMAC0_AXI 0 146 #define JH7110_AONRST_GMAC0_AHB 1 147 #define JH7110_AONRST_IOMUX 2 148 #define JH7110_AONRST_PMU_APB 3 149 #define JH7110_AONRST_PMU_WKUP 4 150 #define JH7110_AONRST_RTC_APB 5 151 #define JH7110_AONRST_RTC_CAL 6 152 #define JH7110_AONRST_RTC_32K 7 153 154 #define JH7110_AONRST_END 8 155 156 /* STGCRG resets */ 157 #define JH7110_STGRST_SYSCON_PRESETN 0 158 #define JH7110_STGRST_HIFI4_CORE 1 159 #define JH7110_STGRST_HIFI4_AXI 2 160 #define JH7110_STGRST_SEC_TOP_HRESETN 3 161 #define JH7110_STGRST_E24_CORE 4 162 #define JH7110_STGRST_DMA1P_AXI 5 163 #define JH7110_STGRST_DMA1P_AHB 6 164 #define JH7110_STGRST_USB_AXI 7 165 #define JH7110_STGRST_USB_APB 8 166 #define JH7110_STGRST_USB_UTMI_APB 9 167 #define JH7110_STGRST_USB_PWRUP 10 168 #define JH7110_STGRST_PCIE0_MST0 11 169 #define JH7110_STGRST_PCIE0_SLV0 12 170 #define JH7110_STGRST_PCIE0_SLV 13 171 #define JH7110_STGRST_PCIE0_BRG 14 172 #define JH7110_STGRST_PCIE0_CORE 15 173 #define JH7110_STGRST_PCIE0_APB 16 174 #define JH7110_STGRST_PCIE1_MST0 17 175 #define JH7110_STGRST_PCIE1_SLV0 18 176 #define JH7110_STGRST_PCIE1_SLV 19 177 #define JH7110_STGRST_PCIE1_BRG 20 178 #define JH7110_STGRST_PCIE1_CORE 21 179 #define JH7110_STGRST_PCIE1_APB 22 180 181 #define JH7110_STGRST_END 23 182 183 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ 184