1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <handoff.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/fsp/fsp_support.h>
11 #include <asm/e820.h>
12 #include <asm/global_data.h>
13 #include <asm/mrccache.h>
14 #include <asm/mtrr.h>
15 #include <asm/post.h>
16 #include <dm/ofnode.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
fsp_scan_for_ram_size(void)20 int fsp_scan_for_ram_size(void)
21 {
22 phys_size_t ram_size = 0;
23 const struct hob_header *hdr;
24 struct hob_res_desc *res_desc;
25
26 hdr = gd->arch.hob_list;
27 while (!end_of_hob(hdr)) {
28 if (hdr->type == HOB_TYPE_RES_DESC) {
29 res_desc = (struct hob_res_desc *)hdr;
30 if (res_desc->type == RES_SYS_MEM ||
31 res_desc->type == RES_MEM_RESERVED)
32 ram_size += res_desc->len;
33 }
34 hdr = get_next_hob(hdr);
35 }
36
37 gd->ram_size = ram_size;
38 post_code(POST_DRAM);
39
40 return 0;
41 };
42
dram_init_banksize(void)43 int dram_init_banksize(void)
44 {
45 efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
46 const struct hob_header *hdr;
47 struct hob_res_desc *res_desc;
48 phys_addr_t mtrr_top;
49 phys_addr_t low_end;
50 uint bank;
51 bool update_mtrr;
52
53 /*
54 * For FSP1, the system memory and reserved memory used by FSP are
55 * already programmed in the MTRR by FSP. Also it is observed that
56 * FSP on Intel Queensbay platform reports the TSEG memory range
57 * that has the same RES_MEM_RESERVED resource type whose address
58 * is programmed by FSP to be near the top of 4 GiB space, which is
59 * not what we want for DRAM.
60 *
61 * However it seems FSP2's behavior is different. We need to add the
62 * DRAM range in MTRR otherwise the boot process goes very slowly,
63 * which was observed on Chromebook Coral with FSP2.
64 */
65 update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
66
67 if (!ll_boot_init()) {
68 gd->bd->bi_dram[0].start = 0;
69 gd->bd->bi_dram[0].size = gd->ram_size;
70
71 if (update_mtrr)
72 mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
73 return 0;
74 }
75
76 low_end = 0; /* top of low memory usable by U-Boot */
77 mtrr_top = 0; /* top of low memory (even if reserved) */
78 for (bank = 1, hdr = gd->arch.hob_list;
79 bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
80 hdr = get_next_hob(hdr)) {
81 if (hdr->type != HOB_TYPE_RES_DESC)
82 continue;
83 res_desc = (struct hob_res_desc *)hdr;
84 if (!guidcmp(&res_desc->owner, &fsp))
85 low_end = res_desc->phys_start;
86 if (res_desc->type != RES_SYS_MEM &&
87 res_desc->type != RES_MEM_RESERVED)
88 continue;
89 if (res_desc->phys_start < (1ULL << 32)) {
90 mtrr_top = max(mtrr_top,
91 res_desc->phys_start + res_desc->len);
92 } else {
93 gd->bd->bi_dram[bank].start = res_desc->phys_start;
94 gd->bd->bi_dram[bank].size = res_desc->len;
95 if (update_mtrr)
96 mtrr_add_request(MTRR_TYPE_WRBACK,
97 res_desc->phys_start,
98 res_desc->len);
99 log_debug("ram %llx %llx\n",
100 gd->bd->bi_dram[bank].start,
101 gd->bd->bi_dram[bank].size);
102 }
103 }
104
105 /* Add the memory below 4GB */
106 gd->bd->bi_dram[0].start = 0;
107 gd->bd->bi_dram[0].size = low_end;
108
109 /*
110 * Set up an MTRR to the top of low, reserved memory. This is necessary
111 * for graphics to run at full speed in U-Boot.
112 */
113 if (update_mtrr)
114 mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
115
116 return 0;
117 }
118
install_e820_map(unsigned int max_entries,struct e820_entry * entries)119 unsigned int install_e820_map(unsigned int max_entries,
120 struct e820_entry *entries)
121 {
122 unsigned int num_entries = 0;
123 const struct hob_header *hdr;
124 struct hob_res_desc *res_desc;
125 const fdt64_t *prop;
126 int size;
127
128 hdr = gd->arch.hob_list;
129
130 while (!end_of_hob(hdr)) {
131 if (hdr->type == HOB_TYPE_RES_DESC) {
132 res_desc = (struct hob_res_desc *)hdr;
133 entries[num_entries].addr = res_desc->phys_start;
134 entries[num_entries].size = res_desc->len;
135
136 if (res_desc->type == RES_SYS_MEM)
137 entries[num_entries].type = E820_RAM;
138 else if (res_desc->type == RES_MEM_RESERVED)
139 entries[num_entries].type = E820_RESERVED;
140
141 num_entries++;
142 }
143 hdr = get_next_hob(hdr);
144 }
145
146 /* Mark PCIe ECAM address range as reserved */
147 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
148 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
149 entries[num_entries].type = E820_RESERVED;
150 num_entries++;
151
152 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
153 ulong stack_size;
154
155 stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME,
156 (CONFIG_STACK_SIZE_RESUME), (0));
157 /*
158 * Everything between U-Boot's stack and ram top needs to be
159 * reserved in order for ACPI S3 resume to work.
160 */
161 entries[num_entries].addr = gd->start_addr_sp - stack_size;
162 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
163 stack_size;
164 entries[num_entries].type = E820_RESERVED;
165 num_entries++;
166 }
167
168 prop = ofnode_read_chosen_prop("e820-entries", &size);
169 if (prop) {
170 int count = size / (sizeof(u64) * 3);
171 int i;
172
173 if (num_entries + count >= max_entries)
174 return -ENOSPC;
175 for (i = 0; i < count; i++, num_entries++, prop += 3) {
176 entries[num_entries].addr = fdt64_to_cpu(prop[0]);
177 entries[num_entries].size = fdt64_to_cpu(prop[1]);
178 entries[num_entries].type = fdt64_to_cpu(prop[2]);
179 }
180 }
181
182 return num_entries;
183 }
184
185 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
handoff_arch_save(struct spl_handoff * ho)186 int handoff_arch_save(struct spl_handoff *ho)
187 {
188 ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
189 ho->arch.hob_list = gd->arch.hob_list;
190
191 return 0;
192 }
193 #endif
194