1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021-2022 Stefan Roese <sr@denx.de>
4 */
5
6 #include <cyclic.h>
7 #include <dm.h>
8 #include <ram.h>
9 #include <time.h>
10 #include <asm/gpio.h>
11
12 #include <mach/octeon_ddr.h>
13 #include <mach/cvmx-qlm.h>
14 #include <mach/octeon_qlm.h>
15 #include <mach/octeon_fdt.h>
16 #include <mach/cvmx-helper.h>
17 #include <mach/cvmx-helper-cfg.h>
18 #include <mach/cvmx-helper-util.h>
19 #include <mach/cvmx-bgxx-defs.h>
20 #include <mach/cvmx-dtx-defs.h>
21
22 #include "board_ddr.h"
23
24 /**
25 * cvmx_spem#_cfg_rd
26 *
27 * This register allows read access to the configuration in the PCIe core.
28 *
29 */
30 union cvmx_spemx_cfg_rd {
31 u64 u64;
32 struct cvmx_spemx_cfg_rd_s {
33 u64 data : 32;
34 u64 addr : 32;
35 } s;
36 struct cvmx_spemx_cfg_rd_s cn73xx;
37 };
38
39 /**
40 * cvmx_spem#_cfg_wr
41 *
42 * This register allows write access to the configuration in the PCIe core.
43 *
44 */
45 union cvmx_spemx_cfg_wr {
46 u64 u64;
47 struct cvmx_spemx_cfg_wr_s {
48 u64 data : 32;
49 u64 addr : 32;
50 } s;
51 struct cvmx_spemx_cfg_wr_s cn73xx;
52 };
53
54 /**
55 * cvmx_spem#_flr_pf_stopreq
56 *
57 * PF function level reset stop outbound requests register.
58 * Hardware automatically sets the STOPREQ bit for the PF when it enters a
59 * function level reset (FLR). Software is responsible for clearing the STOPREQ
60 * bit but must not do so prior to hardware taking down the FLR, which could be
61 * as long as 100ms. It may be appropriate for software to wait longer before clearing
62 * STOPREQ, software may need to drain deep DPI queues for example.
63 * Whenever SPEM receives a PF or child VF request mastered by CNXXXX over S2M (i.e. P or NP),
64 * when STOPREQ is set for the function, SPEM will discard the outgoing request
65 * before sending it to the PCIe core. If a NP, SPEM will schedule an immediate
66 * SWI_RSP_ERROR completion for the request - no timeout is required.
67 * In both cases, SPEM()_DBG_PF()_INFO[P()_BMD_E] will be set and a error
68 * interrupt is generated.
69 *
70 * STOPREQ mimics the behavior of PCIEEP()_CFG001[ME] for outbound requests that will
71 * master the PCIe bus (P and NP).
72 *
73 * STOPREQ will have no effect on completions returned by CNXXXX over the S2M,
74 * nor on M2S traffic.
75 *
76 * When a PF()_STOPREQ is set, none of the associated
77 * PEM()_FLR_PF()_VF_STOPREQ[VF_STOPREQ] will be set.
78 *
79 * STOPREQ is reset when the MAC is reset, and is not reset after a chip soft reset.
80 */
81 union cvmx_spemx_flr_pf_stopreq {
82 u64 u64;
83 struct cvmx_spemx_flr_pf_stopreq_s {
84 u64 reserved_3_63 : 61;
85 u64 pf2_stopreq : 1;
86 u64 pf1_stopreq : 1;
87 u64 pf0_stopreq : 1;
88 } s;
89 struct cvmx_spemx_flr_pf_stopreq_s cn73xx;
90 };
91
92 #define CVMX_SPEMX_CFG_WR(offset) 0x00011800C0000028ull
93 #define CVMX_SPEMX_CFG_RD(offset) 0x00011800C0000030ull
94 #define CVMX_SPEMX_FLR_PF_STOPREQ(offset) 0x00011800C0000218ull
95
96 #define DTX_SELECT_LTSSM 0x0
97 #define DTX_SELECT_LTSSM_ENA 0x3ff
98 #define LTSSM_L0 0x11
99
100 #define NIC23_DEF_DRAM_FREQ 800
101
102 static u32 pci_cfgspace_reg0[2] = { 0, 0 };
103
104 static u8 octeon_nic23_cfg0_spd_values[512] = {
105 OCTEON_NIC23_CFG0_SPD_VALUES
106 };
107
108 static struct ddr_conf board_ddr_conf[] = {
109 OCTEON_NIC23_DDR_CONFIGURATION
110 };
111
octeon_ddr_conf_table_get(int * count,int * def_ddr_freq)112 struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
113 {
114 *count = ARRAY_SIZE(board_ddr_conf);
115 *def_ddr_freq = NIC23_DEF_DRAM_FREQ;
116
117 return board_ddr_conf;
118 }
119
board_fix_fdt(void * fdt)120 int board_fix_fdt(void *fdt)
121 {
122 u32 range_data[5 * 8];
123 bool rev4;
124 int node;
125 int rc;
126
127 /*
128 * ToDo:
129 * Read rev4 info from EEPROM or where the original U-Boot does
130 * and don't hard-code it here.
131 */
132 rev4 = true;
133
134 debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false");
135 /* Patch the PHY configuration based on board revision */
136 rc = octeon_fdt_patch_rename(fdt,
137 rev4 ? "4,nor-flash" : "4,no-nor-flash",
138 "cavium,board-trim", false, NULL, NULL);
139 if (!rev4) {
140 /* Modify the ranges for CS 0 */
141 node = fdt_node_offset_by_compatible(fdt, -1,
142 "cavium,octeon-3860-bootbus");
143 if (node < 0) {
144 printf("%s: Error: cannot find boot bus in device tree!\n",
145 __func__);
146 return -1;
147 }
148
149 rc = fdtdec_get_int_array(fdt, node, "ranges",
150 range_data, 5 * 8);
151 if (rc) {
152 printf("%s: Error reading ranges from boot bus FDT\n",
153 __func__);
154 return -1;
155 }
156 range_data[2] = cpu_to_fdt32(0x10000);
157 range_data[3] = 0;
158 range_data[4] = 0;
159 rc = fdt_setprop(fdt, node, "ranges", range_data,
160 sizeof(range_data));
161 if (rc) {
162 printf("%s: Error updating boot bus ranges in fdt\n",
163 __func__);
164 }
165 }
166 return rc;
167 }
168
board_early_init_f(void)169 int board_early_init_f(void)
170 {
171 struct gpio_desc gpio = {};
172 ofnode node;
173
174 /* Initial GPIO configuration */
175
176 /* GPIO 7: Vitesse reset */
177 node = ofnode_by_compatible(ofnode_null(), "vitesse,vsc7224");
178 if (ofnode_valid(node)) {
179 gpio_request_by_name_nodev(node, "los", 0, &gpio, GPIOD_IS_IN);
180 dm_gpio_free(gpio.dev, &gpio);
181 gpio_request_by_name_nodev(node, "reset", 0, &gpio,
182 GPIOD_IS_OUT);
183 if (dm_gpio_is_valid(&gpio)) {
184 /* Vitesse reset */
185 debug("%s: Setting GPIO 7 to 1\n", __func__);
186 dm_gpio_set_value(&gpio, 1);
187 }
188 dm_gpio_free(gpio.dev, &gpio);
189 }
190
191 /* SFP+ transmitters */
192 ofnode_for_each_compatible_node(node, "ethernet,sfp-slot") {
193 gpio_request_by_name_nodev(node, "tx_disable", 0,
194 &gpio, GPIOD_IS_OUT);
195 if (dm_gpio_is_valid(&gpio)) {
196 debug("%s: Setting GPIO %d to 1\n", __func__,
197 gpio.offset);
198 dm_gpio_set_value(&gpio, 1);
199 }
200 dm_gpio_free(gpio.dev, &gpio);
201 gpio_request_by_name_nodev(node, "mod_abs", 0, &gpio,
202 GPIOD_IS_IN);
203 dm_gpio_free(gpio.dev, &gpio);
204 gpio_request_by_name_nodev(node, "tx_error", 0, &gpio,
205 GPIOD_IS_IN);
206 dm_gpio_free(gpio.dev, &gpio);
207 gpio_request_by_name_nodev(node, "rx_los", 0, &gpio,
208 GPIOD_IS_IN);
209 dm_gpio_free(gpio.dev, &gpio);
210 }
211
212 return 0;
213 }
214
board_configure_qlms(void)215 void board_configure_qlms(void)
216 {
217 octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0);
218 octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0);
219 /* Apply amplitude tuning to 10G interface */
220 octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1);
221 octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1);
222 octeon_qlm_set_channel_v3(0, 5, 0);
223 octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2);
224 debug("QLM 4 reference clock: %d\n"
225 "DLM 5 reference clock: %d\n",
226 cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5));
227 }
228
229 /**
230 * If there is a PF FLR then the PCI EEPROM is not re-read. In this case
231 * we need to re-program the vendor and device ID immediately after hardware
232 * completes FLR.
233 *
234 * PCI spec requires FLR to be completed within 100ms. The user who triggered
235 * FLR expects hardware to finish FLR within 100ms, otherwise the user will
236 * end up reading DEVICE_ID incorrectly from the reset value.
237 * CN23XX exits FLR at any point between 66 and 99ms, so U-Boot has to wait
238 * 99ms to let hardware finish its part, then finish reprogramming the
239 * correct device ID before the end of 100ms.
240 *
241 * Note: this solution only works properly when there is no other activity
242 * within U-Boot for 100ms from the time FLR is triggered.
243 *
244 * This function gets called every 100usec. If FLR happens during any
245 * other activity like bootloader/image update then it is possible that
246 * this function does not get called for more than the FLR period which will
247 * cause the PF device ID restore to happen after whoever initiated the FLR to
248 * read the incorrect device ID 0x9700 (reset value) instead of 0x9702
249 * (restored value).
250 */
octeon_board_restore_pf(void * ctx)251 static void octeon_board_restore_pf(void *ctx)
252 {
253 union cvmx_spemx_flr_pf_stopreq stopreq;
254 static bool start_initialized[2] = {false, false};
255 bool pf0_flag, pf1_flag;
256 u64 ltssm_bits;
257 const u64 pf_flr_wait_usecs = 99700;
258 u64 elapsed_usecs;
259 union cvmx_spemx_cfg_wr cfg_wr;
260 union cvmx_spemx_cfg_rd cfg_rd;
261 static u64 start_us[2];
262 int pf_num;
263
264 csr_wr(CVMX_DTX_SPEM_SELX(0), DTX_SELECT_LTSSM);
265 csr_rd(CVMX_DTX_SPEM_SELX(0));
266 csr_wr(CVMX_DTX_SPEM_ENAX(0), DTX_SELECT_LTSSM_ENA);
267 csr_rd(CVMX_DTX_SPEM_ENAX(0));
268 ltssm_bits = csr_rd(CVMX_DTX_SPEM_DATX(0));
269 if (((ltssm_bits >> 3) & 0x3f) != LTSSM_L0)
270 return;
271
272 stopreq.u64 = csr_rd(CVMX_SPEMX_FLR_PF_STOPREQ(0));
273 pf0_flag = stopreq.s.pf0_stopreq;
274 pf1_flag = stopreq.s.pf1_stopreq;
275 /* See if PF interrupt happened */
276 if (!(pf0_flag || pf1_flag))
277 return;
278
279 if (pf0_flag && !start_initialized[0]) {
280 start_initialized[0] = true;
281 start_us[0] = get_timer_us(0);
282 }
283
284 /* Store programmed PCIe DevID SPEM0 PF0 */
285 if (pf0_flag && !pci_cfgspace_reg0[0]) {
286 cfg_rd.s.addr = (0 << 24) | 0x0;
287 csr_wr(CVMX_SPEMX_CFG_RD(0), cfg_rd.u64);
288 cfg_rd.u64 = csr_rd(CVMX_SPEMX_CFG_RD(0));
289 pci_cfgspace_reg0[0] = cfg_rd.s.data;
290 }
291
292 if (pf1_flag && !start_initialized[1]) {
293 start_initialized[1] = true;
294 start_us[1] = get_timer_us(0);
295 }
296
297 /* Store programmed PCIe DevID SPEM0 PF1 */
298 if (pf1_flag && !pci_cfgspace_reg0[1]) {
299 cfg_rd.s.addr = (1 << 24) | 0x0;
300 csr_wr(CVMX_SPEMX_CFG_RD(0), cfg_rd.u64);
301 cfg_rd.u64 = csr_rd(CVMX_SPEMX_CFG_RD(0));
302 pci_cfgspace_reg0[1] = cfg_rd.s.data;
303 }
304
305 /* For PF, rewrite pci config space reg 0 */
306 for (pf_num = 0; pf_num < 2; pf_num++) {
307 if (!start_initialized[pf_num])
308 continue;
309
310 elapsed_usecs = get_timer_us(0) - start_us[pf_num];
311
312 if (elapsed_usecs > pf_flr_wait_usecs) {
313 /* Here, our measured FLR duration has passed;
314 * check if device ID has been reset,
315 * which indicates FLR completion (per MA team).
316 */
317 cfg_rd.s.addr = (pf_num << 24) | 0x0;
318 csr_wr(CVMX_SPEMX_CFG_RD(0), cfg_rd.u64);
319 cfg_rd.u64 = csr_rd(CVMX_SPEMX_CFG_RD(0));
320 /* if DevID has NOT been reset, FLR is not yet
321 * complete
322 */
323 if (cfg_rd.s.data != pci_cfgspace_reg0[pf_num]) {
324 stopreq.s.pf0_stopreq = (pf_num == 0) ? 1 : 0;
325 stopreq.s.pf1_stopreq = (pf_num == 1) ? 1 : 0;
326 csr_wr(CVMX_SPEMX_FLR_PF_STOPREQ(0), stopreq.u64);
327
328 cfg_wr.u64 = 0;
329 cfg_wr.s.addr = (pf_num << 24) | 0;
330 cfg_wr.s.data = pci_cfgspace_reg0[pf_num];
331 csr_wr(CVMX_SPEMX_CFG_WR(0), cfg_wr.u64);
332 start_initialized[pf_num] = false;
333 }
334 }
335 }
336 }
337
board_late_init(void)338 int board_late_init(void)
339 {
340 struct cyclic_info *cyclic;
341 struct gpio_desc gpio = {};
342 ofnode node;
343
344 /* Turn on SFP+ transmitters */
345 ofnode_for_each_compatible_node(node, "ethernet,sfp-slot") {
346 gpio_request_by_name_nodev(node, "tx_disable", 0,
347 &gpio, GPIOD_IS_OUT);
348 if (dm_gpio_is_valid(&gpio)) {
349 debug("%s: Setting GPIO %d to 0\n", __func__,
350 gpio.offset);
351 dm_gpio_set_value(&gpio, 0);
352 }
353 dm_gpio_free(gpio.dev, &gpio);
354 }
355
356 board_configure_qlms();
357
358 /* Register cyclic function for PCIe FLR fixup */
359 cyclic = cyclic_register(octeon_board_restore_pf, 100,
360 "pcie_flr_fix", NULL);
361 if (!cyclic)
362 printf("Registering of cyclic function failed\n");
363
364 return 0;
365 }
366
last_stage_init(void)367 int last_stage_init(void)
368 {
369 struct gpio_desc gpio = {};
370 ofnode node;
371
372 node = ofnode_by_compatible(ofnode_null(), "vitesse,vsc7224");
373 if (!ofnode_valid(node)) {
374 printf("Vitesse SPF DT node not found!");
375 return 0;
376 }
377
378 gpio_request_by_name_nodev(node, "reset", 0, &gpio, GPIOD_IS_OUT);
379 if (dm_gpio_is_valid(&gpio)) {
380 /* Take Vitesse retimer out of reset */
381 debug("%s: Setting GPIO 7 to 0\n", __func__);
382 dm_gpio_set_value(&gpio, 0);
383 mdelay(50);
384 }
385 dm_gpio_free(gpio.dev, &gpio);
386
387 return 0;
388 }
389