1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <init.h>
11 #include <net.h>
12 #include <vsprintf.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/at91sam9g45_matrix.h>
17 #include <asm/arch/at91sam9_smc.h>
18 #include <asm/arch/at91_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clk.h>
21 #include <linux/mtd/rawnand.h>
22 #include <atmel_lcdc.h>
23 #include <asm/mach-types.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 /* ------------------------------------------------------------------------- */
28 /*
29 * Miscelaneous platform dependent initialisations
30 */
31
32 #ifdef CONFIG_CMD_NAND
at91sam9m10g45ek_nand_hw_init(void)33 void at91sam9m10g45ek_nand_hw_init(void)
34 {
35 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
37 unsigned long csa;
38
39 /* Enable CS3 */
40 csa = readl(&matrix->ebicsa);
41 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
42 writel(csa, &matrix->ebicsa);
43
44 /* Configure SMC CS3 for NAND/SmartMedia */
45 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
46 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
47 &smc->cs[3].setup);
48 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
49 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
50 &smc->cs[3].pulse);
51 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
52 &smc->cs[3].cycle);
53 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
54 AT91_SMC_MODE_EXNW_DISABLE |
55 #ifdef CONFIG_SYS_NAND_DBW_16
56 AT91_SMC_MODE_DBW_16 |
57 #else /* CONFIG_SYS_NAND_DBW_8 */
58 AT91_SMC_MODE_DBW_8 |
59 #endif
60 AT91_SMC_MODE_TDF_CYCLE(3),
61 &smc->cs[3].mode);
62
63 at91_periph_clk_enable(ATMEL_ID_PIOC);
64
65 /* Configure RDY/BSY */
66 at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
67
68 /* Enable NandFlash */
69 at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
70 }
71 #endif
72
73 #if defined(CONFIG_SPL_BUILD)
74 #include <spl.h>
75 #include <nand.h>
76
at91_spl_board_init(void)77 void at91_spl_board_init(void)
78 {
79 /*
80 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
81 * test mode, so it needs do some action to exit test mode.
82 */
83 at91_periph_clk_enable(ATMEL_ID_PIODE);
84 at91_set_gpio_output(AT91_PIN_PD7, 0);
85 at91_set_gpio_output(AT91_PIN_PD8, 0);
86 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
87 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
88
89 #ifdef CONFIG_SD_BOOT
90 at91_mci_hw_init();
91 #elif CONFIG_NAND_BOOT
92 at91sam9m10g45ek_nand_hw_init();
93 #endif
94 }
95
96 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)97 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
98 {
99 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
100
101 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
102 ATMEL_MPDDRC_CR_NR_ROW_14 |
103 ATMEL_MPDDRC_CR_DQMS_SHARED |
104 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
105
106 ddr2->rtr = 0x24b;
107
108 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
109 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
110 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
111 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
112 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
113 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
114 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
115 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
116
117 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
118 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
119 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
120 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
121
122 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
123 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
124 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
125 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
126 }
127
mem_init(void)128 void mem_init(void)
129 {
130 struct atmel_mpddrc_config ddr2;
131
132 ddr2_conf(&ddr2);
133
134 at91_system_clk_enable(AT91_PMC_DDR);
135
136 /* DDRAM2 Controller initialize */
137 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
138 }
139 #endif
140
141 #ifdef CONFIG_CMD_USB
at91sam9m10g45ek_usb_hw_init(void)142 static void at91sam9m10g45ek_usb_hw_init(void)
143 {
144 at91_periph_clk_enable(ATMEL_ID_PIODE);
145
146 at91_set_gpio_output(AT91_PIN_PD1, 0);
147 at91_set_gpio_output(AT91_PIN_PD3, 0);
148 }
149 #endif
150
151 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)152 void board_debug_uart_init(void)
153 {
154 at91_seriald_hw_init();
155 }
156 #endif
157
158 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)159 int board_early_init_f(void)
160 {
161 return 0;
162 }
163 #endif
164
board_init(void)165 int board_init(void)
166 {
167 /* arch number of AT91SAM9M10G45EK-Board */
168 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
169
170 /* adress of boot parameters */
171 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
172
173 #ifdef CONFIG_CMD_NAND
174 at91sam9m10g45ek_nand_hw_init();
175 #endif
176 #ifdef CONFIG_CMD_USB
177 at91sam9m10g45ek_usb_hw_init();
178 #endif
179 return 0;
180 }
181
dram_init(void)182 int dram_init(void)
183 {
184 gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
185 CFG_SYS_SDRAM_SIZE);
186 return 0;
187 }
188
189 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)190 void reset_phy(void)
191 {
192 }
193 #endif
194