1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 - 2013 Atmel Corporation
4 * Bo Shen <voice.shen@atmel.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/sama5d3_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
16 #include <debug_uart.h>
17 #include <env.h>
18 #include <linux/ctype.h>
19 #include <spl.h>
20 #include <asm/arch/atmel_mpddrc.h>
21 #include <asm/arch/at91_wdt.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* ------------------------------------------------------------------------- */
26 /*
27 * Miscelaneous platform dependent initialisations
28 */
29
30 #ifdef CONFIG_NAND_ATMEL
sama5d3xek_nand_hw_init(void)31 void sama5d3xek_nand_hw_init(void)
32 {
33 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
34
35 at91_periph_clk_enable(ATMEL_ID_SMC);
36
37 /* Configure SMC CS3 for NAND/SmartMedia */
38 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
39 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
40 &smc->cs[3].setup);
41 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
42 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
43 &smc->cs[3].pulse);
44 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
45 &smc->cs[3].cycle);
46 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
47 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
48 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
49 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
50 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
51 AT91_SMC_MODE_EXNW_DISABLE |
52 #ifdef CONFIG_SYS_NAND_DBW_16
53 AT91_SMC_MODE_DBW_16 |
54 #else /* CONFIG_SYS_NAND_DBW_8 */
55 AT91_SMC_MODE_DBW_8 |
56 #endif
57 AT91_SMC_MODE_TDF_CYCLE(3),
58 &smc->cs[3].mode);
59 }
60 #endif
61
62 #ifdef CONFIG_MTD_NOR_FLASH
sama5d3xek_nor_hw_init(void)63 static void sama5d3xek_nor_hw_init(void)
64 {
65 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
66
67 at91_periph_clk_enable(ATMEL_ID_SMC);
68
69 /* Configure SMC CS0 for NOR flash */
70 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
71 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
72 &smc->cs[0].setup);
73 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
74 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
75 &smc->cs[0].pulse);
76 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
77 &smc->cs[0].cycle);
78 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
79 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
80 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
81 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
82 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
83 AT91_SMC_MODE_EXNW_DISABLE |
84 AT91_SMC_MODE_DBW_16 |
85 AT91_SMC_MODE_TDF_CYCLE(1),
86 &smc->cs[0].mode);
87
88 /* Address pin (A1 ~ A23) configuration */
89 at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
90 at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
91 at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
92 at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
93 at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
94 at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
95 at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
96 at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
97 at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
98 at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
99 at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
100 at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
101 at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
102 at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
103 at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
104 at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
105 at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
106 at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
107 at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
108 at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
109 at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
110 at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
111 at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
112 /* CS0 pin configuration */
113 at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
114 }
115 #endif
116
117 #ifdef CONFIG_CMD_USB
sama5d3xek_usb_hw_init(void)118 static void sama5d3xek_usb_hw_init(void)
119 {
120 at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
121 at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
122 at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
123 }
124 #endif
125
126 #ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3xek_mci_hw_init(void)127 static void sama5d3xek_mci_hw_init(void)
128 {
129 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
130 }
131 #endif
132
133 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)134 void board_debug_uart_init(void)
135 {
136 at91_seriald_hw_init();
137 }
138 #endif
139
140 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)141 int board_early_init_f(void)
142 {
143 return 0;
144 }
145 #endif
146
board_init(void)147 int board_init(void)
148 {
149 /* adress of boot parameters */
150 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
151
152 #ifdef CONFIG_NAND_ATMEL
153 sama5d3xek_nand_hw_init();
154 #endif
155 #ifdef CONFIG_MTD_NOR_FLASH
156 sama5d3xek_nor_hw_init();
157 #endif
158 #ifdef CONFIG_CMD_USB
159 sama5d3xek_usb_hw_init();
160 #endif
161 #ifdef CONFIG_GENERIC_ATMEL_MCI
162 sama5d3xek_mci_hw_init();
163 #endif
164 return 0;
165 }
166
dram_init(void)167 int dram_init(void)
168 {
169 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
170 CFG_SYS_SDRAM_SIZE);
171 return 0;
172 }
173
174 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)175 int board_late_init(void)
176 {
177 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
178 const int MAX_STR_LEN = 32;
179 char name[MAX_STR_LEN], *p;
180 int i;
181
182 strncpy(name, get_cpu_name(), MAX_STR_LEN);
183 for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
184 *p = tolower(*p);
185
186 strcat(name, "ek.dtb");
187 env_set("dtb_name", name);
188 #endif
189 #ifdef CONFIG_VIDEO
190 at91_video_show_board_info();
191 #endif
192 return 0;
193 }
194 #endif
195
196 /* SPL */
197 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)198 void spl_board_init(void)
199 {
200 #if CONFIG_NAND_BOOT
201 sama5d3xek_nand_hw_init();
202 #endif
203 }
204
ddr2_conf(struct atmel_mpddrc_config * ddr2)205 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
206 {
207 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
208
209 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
210 ATMEL_MPDDRC_CR_NR_ROW_14 |
211 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
212 ATMEL_MPDDRC_CR_ENRDM_ON |
213 ATMEL_MPDDRC_CR_NB_8BANKS |
214 ATMEL_MPDDRC_CR_NDQS_DISABLED |
215 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
216 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
217 /*
218 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
219 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
220 */
221 ddr2->rtr = 0x411;
222
223 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
224 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
225 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
226 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
227 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
228 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
229 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
230 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
231
232 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
233 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
234 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
235 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
236
237 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
238 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
239 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
240 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
241 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
242 }
243
mem_init(void)244 void mem_init(void)
245 {
246 struct atmel_mpddrc_config ddr2;
247
248 ddr2_conf(&ddr2);
249
250 /* Enable MPDDR clock */
251 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
252 at91_system_clk_enable(AT91_PMC_DDR);
253
254 /* DDRAM2 Controller initialize */
255 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
256 }
257
at91_pmc_init(void)258 void at91_pmc_init(void)
259 {
260 u32 tmp;
261
262 tmp = AT91_PMC_PLLAR_29 |
263 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
264 AT91_PMC_PLLXR_MUL(43) |
265 AT91_PMC_PLLXR_DIV(1);
266 at91_plla_init(tmp);
267
268 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
269
270 tmp = AT91_PMC_MCKR_MDIV_4 |
271 AT91_PMC_MCKR_CSS_PLLA;
272 at91_mck_init(tmp);
273 }
274 #endif
275