1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 * Copyright 2020 Linaro
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <cpu_func.h>
10 #include <hang.h>
11 #include <image.h>
12 #include <init.h>
13 #include <log.h>
14 #include <spl.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx8mm_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/gpio.h>
23 #include <asm/arch/ddr.h>
24
25 #include <dm/uclass.h>
26 #include <dm/device.h>
27 #include <dm/uclass-internal.h>
28 #include <dm/device-internal.h>
29
30 #include <power/pmic.h>
31 #include <power/bd71837.h>
32
33 #include "ddr/ddr.h"
34
35 DECLARE_GLOBAL_DATA_PTR;
36
spl_board_boot_device(enum boot_device boot_dev_spl)37 int spl_board_boot_device(enum boot_device boot_dev_spl)
38 {
39 switch (boot_dev_spl) {
40 case SD2_BOOT:
41 case MMC2_BOOT:
42 return BOOT_DEVICE_MMC1;
43 case SD3_BOOT:
44 case MMC3_BOOT:
45 return BOOT_DEVICE_MMC2;
46 default:
47 return BOOT_DEVICE_NONE;
48 }
49 }
50
51 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
52 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
53 struct i2c_pads_info i2c_pad_info1 = {
54 .scl = {
55 .i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC,
56 .gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC,
57 .gp = IMX_GPIO_NR(5, 16),
58 },
59 .sda = {
60 .i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC,
61 .gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC,
62 .gp = IMX_GPIO_NR(5, 17),
63 },
64 };
65
spl_dram_init(void)66 static void spl_dram_init(void)
67 {
68 spl_dram_init_compulab();
69 }
70
spl_board_init(void)71 void spl_board_init(void)
72 {
73 puts("Normal Boot\n");
74 }
75
76 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)77 int board_fit_config_name_match(const char *name)
78 {
79 /* Just empty function now - can't decide what to choose */
80 debug("%s: %s\n", __func__, name);
81
82 return 0;
83 }
84 #endif
85
power_init_board(void)86 static int power_init_board(void)
87 {
88 struct udevice *dev;
89 int ret;
90
91 ret = pmic_get("pmic@4b", &dev);
92 if (ret == -ENODEV) {
93 puts("No pmic\n");
94 return 0;
95 }
96 if (ret != 0)
97 return ret;
98
99 /* decrease RESET key long push time from the default 10s to 10ms */
100 pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
101
102 /* unlock the PMIC regs */
103 pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
104
105 /* increase VDD_SOC to typical value 0.85v before first DRAM access */
106 pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
107
108 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
109 pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
110
111 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
112 pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
113
114 /* lock the PMIC regs */
115 pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
116
117 return 0;
118 }
119
board_init_f(ulong dummy)120 void board_init_f(ulong dummy)
121 {
122 struct udevice *dev;
123 int ret;
124
125 arch_cpu_init();
126
127 init_uart_clk(2);
128
129 timer_init();
130
131 /* Clear the BSS. */
132 memset(__bss_start, 0, __bss_end - __bss_start);
133
134 ret = spl_early_init();
135 if (ret) {
136 debug("spl_early_init() failed: %d\n", ret);
137 hang();
138 }
139
140 preloader_console_init();
141
142 ret = uclass_get_device_by_name(UCLASS_CLK,
143 "clock-controller@30380000",
144 &dev);
145 if (ret < 0) {
146 printf("Failed to find clock node. Check device tree\n");
147 hang();
148 }
149
150 enable_tzc380();
151
152 setup_i2c(1, 100000, 0x7f, &i2c_pad_info1);
153
154 power_init_board();
155
156 /* DDR initialization */
157 spl_dram_init();
158
159 board_init_r(NULL, 0);
160 }
161