1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010-2020 CS Group
4 * Charles Frey <charles.frey@c-s.fr>
5 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
6 * Christophe Leroy <christophe.leroy@c-s.fr>
7 *
8 * Board specific routines for the CMPC885 board
9 */
10
11 #include <env.h>
12 #include <common.h>
13 #include <mpc8xx.h>
14 #include <asm/cpm_8xx.h>
15 #include <asm/io.h>
16 #include <dm.h>
17 #include <stdio.h>
18 #include <stdarg.h>
19 #include <watchdog.h>
20 #include <serial.h>
21 #include <hang.h>
22 #include <flash.h>
23 #include <init.h>
24 #include <fdt_support.h>
25 #include <linux/delay.h>
26 #include <spi.h>
27
28 #include "../common/common.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 #define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE)
33 #define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2))
34 #define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)(CONFIG_CPLD_BASE + 3))
35
36 #define PATH_PHY2 "/soc@ff000000/mdio@e00/ethernet-phy@2"
37 #define PATH_PHY3 "/soc@ff000000/mdio@e00/ethernet-phy@3"
38 #define PATH_ETH1 "/soc@ff000000/ethernet@1e00"
39 #define FIBER_PHY PATH_PHY2
40
41 #define R_ETAT_PRES_BASE 0x0040
42
43 #define R_RESET_STATUS 0x0400
44 #define R_RST_STATUS 0x0004
45
ft_board_setup(void * blob,struct bd_info * bd)46 int ft_board_setup(void *blob, struct bd_info *bd)
47 {
48 const char *sync = "receive";
49
50 ft_cpu_setup(blob, bd);
51
52 /* BRG */
53 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", bd->bi_busfreq, 1);
54
55 /* MAC addr */
56 fdt_fixup_ethernet(blob);
57
58 /* Bus Frequency for CPM */
59 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
60
61 /* E1 interface - Set data rate */
62 do_fixup_by_path_u32(blob, "/localbus/e1", "data-rate", 2, 1);
63
64 /* E1 interface - Set channel phase to 0 */
65 do_fixup_by_path_u32(blob, "/localbus/e1", "channel-phase", 0, 1);
66
67 /* E1 interface - rising edge sync pulse transmit */
68 do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse", sync, strlen(sync), 1);
69
70 /* MIAE only */
71 if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE))
72 return 0;
73
74 return ft_board_setup_common(blob);
75 }
76
ft_board_setup_phy3(void)77 void ft_board_setup_phy3(void)
78 {
79 /* switch to phy3 with gpio, we'll only use phy3 */
80 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
81 cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm;
82
83 setbits_be32(&cp->cp_pedat, 0x00002000);
84 }
85
checkboard(void)86 int checkboard(void)
87 {
88 serial_puts("Board: ");
89
90 /* Is a motherboard present ? */
91 if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE)
92 return checkboard_common();
93
94 printf("CMPC885 (CS GROUP)\n");
95
96 return 0;
97 }
98
99 #define MAX_SPI_BYTES 0x20
100
101 #define EE_OFF_MAC1 0x10
102 #define EE_OFF_MAC2 0x16
103
104 /* Reads MAC addresses from SPI EEPROM */
setup_mac(void)105 static int setup_mac(void)
106 {
107 uchar din[MAX_SPI_BYTES];
108 int ret;
109 unsigned long ident = 0x08005120;
110
111 ret = read_eeprom(din, sizeof(din));
112 if (ret)
113 return ret;
114
115 if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0)
116 eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1);
117
118 if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0)
119 eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2);
120
121 return 0;
122 }
123
misc_init_r(void)124 int misc_init_r(void)
125 {
126 /* Verify mother board presence */
127 if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
128 misc_init_r_common();
129 } else {
130 env_set("config", CFG_BOARD_CMPCXXX);
131 env_set("hostname", CFG_BOARD_CMPCXXX);
132 }
133
134 if (setup_mac())
135 printf("Error retrieving mac addresses\n");
136
137 /* Protection ON by default */
138 flash_protect(FLAG_PROTECT_SET, CFG_SYS_FLASH_BASE, 0xffffffff, &flash_info[0]);
139
140 return 0;
141 }
142
iop_setup_mcr(void)143 void iop_setup_mcr(void)
144 {
145 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
146 iop8xx_t __iomem *iop = &immr->im_ioport;
147 cpm8xx_t __iomem *cp = &immr->im_cpm;
148
149 /* Wait reset on FPGA_F */
150 udelay(100);
151
152 /* We must initialize data before changing direction */
153 setbits_be16(&iop->iop_pcdat, 0x088E);
154 setbits_be16(&iop->iop_pddat, 0x0001);
155 setbits_be32(&cp->cp_pbdat, 0x00029510);
156 setbits_be32(&cp->cp_pedat, 0x00000002);
157
158 /*
159 * PAPAR[13] = 0 [0x0004] -> GPIO: ()
160 * PAPAR[12] = 0 [0x0008] -> GPIO: ()
161 * PAPAR[9] = 1 [0x0040] -> GPIO: (PCM_IN_12_MPC)
162 * PAPAR[8] = 1 [0x0080] -> GPIO: (PCM_OUT_12_MPC)
163 * PAPAR[7] = 1 [0x0100] -> GPIO: (TDM_BCLK_MPC)
164 * PAPAR[6] = 1 [0x0200] -> GPIO: (CLK2)
165 */
166 clrsetbits_be16(&iop->iop_papar, 0x03CC, 0x03C0);
167
168 /*
169 * PBODR[16] = 1 [0x00008000] -> GPIO: (PROG_FPGA_MEZZ)
170 */
171 setbits_be16(&cp->cp_pbodr, 0x00008000);
172
173 /*
174 * PBDIR[27] = 1 [0x00000010] -> GPIO: (WR_TEMP2)
175 * PBDIR[26] = 1 [0x00000020] -> GPIO: (BRG02)
176 * PBDIR[23] = 1 [0x00000100] -> GPIO: (CS_TEMP2)
177 * PBDIR[18] = 1 [0x00002000] -> GPIO: (RTS2)
178 * PBDIR[16] = 1 [0x00008000] -> GPIO: (PROG_FPGA_MEZZ)
179 * PBDIR[15] = 1 [0x00010000] -> GPIO: (BRG03)
180 * PBDIR[14] = 1 [0x00020000] -> GPIO: (CS_TEMP)
181 */
182 setbits_be32(&cp->cp_pbdir, 0x0003A130);
183
184 /*
185 * PBPAR[20] = 1 [0x00000800] -> GPIO: (SMRXD2)
186 * PBPAR[17] = 0 [0x00004000] -> GPIO: (DONE_FPGA_MEZZ)
187 * PBPAR[16] = 0 [0x00008000] -> GPIO: (PROG_FPGA_MEZZ)
188 */
189 clrsetbits_be32(&cp->cp_pbpar, 0x0000C800, 0x00000800);
190
191 /*
192 * PCPAR[14] = 0 [0x0002] -> GPIO: (CS_POT2)
193 */
194 clrbits_be16(&iop->iop_pcpar, 0x0002);
195
196 /*
197 * PDPAR[14] = 1 [0x0002] -> GPIO: (TDM_FS_MPC)
198 * PDPAR[11] = 1 [0x0010] -> GPIO: (RXD3)
199 * PDPAR[10] = 1 [0x0020] -> GPIO: (TXD3)
200 * PDPAR[9] = 1 [0x0040] -> GPIO: (TXD4)
201 * PDPAR[7] = 1 [0x0100] -> GPIO: (RTS3)
202 * PDPAR[5] = 1 [0x0400] -> GPIO: (CLK8)
203 * PDPAR[3] = 1 [0x1000] -> GPIO: (CLK7)
204 */
205 setbits_be16(&iop->iop_pdpar, 0x1572);
206
207 /*
208 * PEPAR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
209 * PEPAR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
210 * PEPAR[25] = 1 [0x00000040] -> GPIO: (RXD4)
211 * PEPAR[24] = 1 [0x00000080] -> GPIO: (BRG01)
212 * PEPAR[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
213 * PEPAR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
214 * PEPAR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
215 * PEPAR[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
216 * PEPAR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
217 * PEPAR[17] = 1 [0x00004000] -> GPIO: (CLK5)
218 * PEPAR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
219 * PEPAR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
220 * PEPAR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
221 */
222 clrsetbits_be32(&cp->cp_pepar, 0x0003DFF0, 0x0003DEF0);
223
224 /*
225 * PADIR[9] = 1 [0x0040] -> GPIO: (PCM_IN_12_MPC)
226 * PADIR[8] = 1 [0x0080] -> GPIO: (PCM_OUT_12_MPC)
227 * PADIR[5] = 1 [0x0400] -> GPIO: ()
228 */
229 setbits_be16(&iop->iop_padir, 0x04C0);
230
231 /*
232 * PCDIR[15] = 1 [0x0001] -> GPIO: (WP_EEPROM2)
233 * PCDIR[14] = 1 [0x0002] -> GPIO: (CS_POT2)
234 * PCDIR[13] = 1 [0x0004] -> GPIO: (CS_POT1)
235 * PCDIR[12] = 1 [0x0008] -> GPIO: (CS_EEPROM2)
236 * PCDIR[8] = 1 [0x0080] -> GPIO: (CS_CODEC_FAV)
237 * PCDIR[4] = 1 [0x0800] -> GPIO: (CS_CODEC_RADIO)
238 */
239 setbits_be16(&iop->iop_pcdir, 0x088F);
240
241 /*
242 * PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
243 * PDDIR[6] = 0 [0x0200] -> GPIO: (INIT_FPGA_RADIO)
244 * PDDIR[2] = x [0x2000] -> Reserved
245 * PDDIR[1] = 0 [0x4000] -> ODR for PD10 : (TXD3)
246 * PDDIR[0] = 0 [0x8000] -> ODR for PD8 : (R_MDC)
247 */
248 clrsetbits_be16(&iop->iop_pddir, 0xC240, 0x0040);
249
250 /*
251 * PEDIR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
252 * PEDIR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
253 * PEDIR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
254 * PEDIR[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
255 * PEDIR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
256 * PEDIR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
257 * PEDIR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
258 * PEDIR[18] = 1 [0x00002000] -> GPIO: (PROG_FPGA_RADIO)
259 * PEDIR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
260 * PEDIR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
261 * PEDIR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
262 */
263 clrsetbits_be32(&cp->cp_pedir, 0x0003B732, 0x0003B632);
264
265 /*
266 * PAODR[10] = 1 [0x0020] -> GPIO: (INIT_FPGA_F)
267 */
268 setbits_be16(&iop->iop_paodr, 0x0020); // set_bit
269
270 /*
271 * PEODR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
272 * PEODR[18] = 1 [0x00002000] -> GPIO: (FPGA_RADIO)
273 */
274 setbits_be32(&cp->cp_peodr, 0x00002002);
275
276 /*
277 * PESO[24] = 1 [0x00000080] -> GPIO: (BRG01)
278 * PESO[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
279 * PESO[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
280 * PESO[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
281 * PESO[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
282 * PESO[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
283 */
284 clrsetbits_be32(&cp->cp_peso, 0x00031980, 0x00031880);
285
286 /* Disable CS for device */
287 /* PROGFPGA down */
288 clrbits_be32(&cp->cp_pbdat, 0x00008000);
289
290 /* PROGFPGA down */
291 clrbits_be32(&cp->cp_pedat, 0x00002000);
292 udelay(1); /* Wait more than 300ns */
293
294 /*
295 * We do not set the PROG signal of the C4E1 because
296 * there is a conflic with the CS of the EEPROM.
297 * I don't know why there is not the same problem
298 * with the FPGA_R
299 */
300
301 /* PROGFPGA up */
302 setbits_be32(&cp->cp_pedat, 0x00002000);
303 }
304
iop_setup_cmpc885(void)305 static void iop_setup_cmpc885(void)
306 {
307 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
308 iop8xx_t __iomem *iop = &immr->im_ioport;
309 cpm8xx_t __iomem *cp = &immr->im_cpm;
310
311 /* We must initialize data before changing direction */
312 out_be16(&iop->iop_pcdat, 0x0000);
313 out_be16(&iop->iop_pddat, 0x0001);
314
315 out_be32(&cp->cp_pbdat, 0x00021400);
316 out_be32(&cp->cp_pedat, 0x00000000);
317
318 /*
319 * PAPAR[13] = 0 [0x0004] -> GPIO: ()
320 * PAPAR[12] = 0 [0x0008] -> GPIO: ()
321 * PAPAR[9] = 0 [0x0040] -> GPIO: ()
322 * PAPAR[8] = 0 [0x0080] -> GPIO: ()
323 * PAPAR[7] = 0 [0x0100] -> GPIO: ()
324 * PAPAR[6] = 0 [0x0200] -> GPIO: ()
325 */
326 clrbits_be16(&iop->iop_papar, 0x03CC);
327
328 /*
329 * PBPAR[20] = 0 [0x00000800] -> GPIO: ()
330 * PBPAR[17] = 0 [0x00004000] -> GPIO: ()
331 * PBPAR[16] = 0 [0x00008000] -> GPIO: ()
332 */
333 clrbits_be32(&cp->cp_pbpar, 0x0000C800);
334
335 /*
336 * PCPAR[14] = 0 [0x0002] -> GPIO: ()
337 */
338 clrbits_be16(&iop->iop_pcpar, 0x0002);
339
340 /*
341 * PDPAR[14] = 0 [0x0002] -> GPIO: ()
342 * PDPAR[11] = 0 [0x0010] -> GPIO: ()
343 * PDPAR[10] = 0 [0x0020] -> GPIO: ()
344 * PDPAR[9] = 0 [0x0040] -> GPIO: ()
345 * PDPAR[7] = 0 [0x0100] -> GPIO: ()
346 * PDPAR[5] = 0 [0x0400] -> GPIO: ()
347 * PDPAR[3] = 0 [0x1000] -> GPIO: ()
348 */
349 clrbits_be16(&iop->iop_pdpar, 0x1572);
350
351 /*
352 * PEPAR[27] = 0 [0x00000010] -> GPIO: ()
353 * PEPAR[26] = 0 [0x00000020] -> GPIO: ()
354 * PEPAR[25] = 0 [0x00000040] -> GPIO: ()
355 * PEPAR[24] = 0 [0x00000080] -> GPIO: ()
356 * PEPAR[23] = 0 [0x00000100] -> GPIO: ()
357 * PEPAR[22] = 0 [0x00000200] -> GPIO: ()
358 * PEPAR[21] = 0 [0x00000400] -> GPIO: ()
359 * PEPAR[20] = 0 [0x00000800] -> GPIO: ()
360 * PEPAR[19] = 0 [0x00001000] -> GPIO: ()
361 * PEPAR[17] = 0 [0x00004000] -> GPIO: ()
362 * PEPAR[16] = 0 [0x00008000] -> GPIO: ()
363 * PEPAR[15] = 0 [0x00010000] -> GPIO: ()
364 * PEPAR[14] = 0 [0x00020000] -> GPIO: ()
365 */
366 clrbits_be32(&cp->cp_pepar, 0x0003DFF0);
367
368 /*
369 * PADIR[9] = 0 [0x0040] -> GPIO: ()
370 * PADIR[8] = 0 [0x0080] -> GPIO: ()
371 * PADIR[5] = 0 [0x0400] -> GPIO: ()
372 */
373 clrbits_be16(&iop->iop_padir, 0x04C0);
374
375 /*
376 * In/Out or per. Function 0/1
377 * PBDIR[27] = 0 [0x00000010] -> GPIO: ()
378 * PBDIR[26] = 0 [0x00000020] -> GPIO: ()
379 * PBDIR[23] = 0 [0x00000100] -> GPIO: ()
380 * PBDIR[17] = 0 [0x00004000] -> GPIO: ()
381 * PBDIR[16] = 0 [0x00008000] -> GPIO: ()
382 */
383 clrbits_be32(&cp->cp_pbdir, 0x0000C130);
384
385 /*
386 * PCDIR[15] = 0 [0x0001] -> GPIO: ()
387 * PCDIR[14] = 0 [0x0002] -> GPIO: ()
388 * PCDIR[13] = 0 [0x0004] -> GPIO: ()
389 * PCDIR[12] = 0 [0x0008] -> GPIO: ()
390 * PCDIR[8] = 0 [0x0080] -> GPIO: ()
391 * PCDIR[4] = 0 [0x0800] -> GPIO: ()
392 */
393 clrbits_be16(&iop->iop_pcdir, 0x088F);
394
395 /*
396 * PDDIR[9] = 0 [0x0040] -> GPIO: ()
397 * PDDIR[6] = 0 [0x0200] -> GPIO: ()
398 * PDDIR[2] = x [0x2000] -> Reserved
399 * PDDIR[1] = 0 [0x4000] -> ODR for PD10 : ()
400 * PDDIR[0] = 0 [0x8000] -> ODR for PD8 : (R_MDC)
401 */
402 clrbits_be16(&iop->iop_pddir, 0xC240);
403
404 /*
405 * PEDIR[30] = 0 [0x00000002] -> GPIO: ()
406 * PEDIR[27] = 0 [0x00000010] -> GPIO: ()
407 * PEDIR[26] = 0 [0x00000020] -> GPIO: ()
408 * PEDIR[23] = 0 [0x00000100] -> GPIO: ()
409 * PEDIR[22] = 0 [0x00000200] -> GPIO: ()
410 * PEDIR[21] = 0 [0x00000400] -> GPIO: ()
411 * PEDIR[19] = 0 [0x00001000] -> GPIO: ()
412 * PEDIR[18] = 0 [0x00002000] -> GPIO: ()
413 * PEDIR[16] = 0 [0x00008000] -> GPIO: ()
414 * PEDIR[15] = 0 [0x00010000] -> GPIO: ()
415 * PEDIR[14] = 0 [0x00020000] -> GPIO: ()
416 */
417 clrbits_be32(&cp->cp_pedir, 0x0003B732);
418
419 /*
420 * PAODR[10] = 0 [0x0020] -> GPIO: ()
421 */
422 clrbits_be16(&iop->iop_paodr, 0x0020);
423
424 /*
425 * PBODR[16] = 0 [0x00008000] -> GPIO: ()
426 */
427 clrbits_be16(&cp->cp_pbodr, 0x00008000);
428
429 /*
430 * PEODR[30] = 0 [0x00000002] -> GPIO: ()
431 * PEODR[18] = 0 [0x00002000] -> GPIO: ()
432 */
433 clrbits_be32(&cp->cp_peodr, 0x00002002);
434
435 /*
436 * PESO[24] = 0 [0x00000080] -> GPIO: ()
437 * PESO[23] = 0 [0x00000100] -> GPIO: ()
438 * PESO[20] = 0 [0x00000800] -> GPIO: ()
439 * PESO[19] = 0 [0x00001000] -> GPIO: ()
440 * PESO[15] = 0 [0x00010000] -> GPIO: ()
441 * PESO[14] = 0 [0x00020000] -> GPIO: ()
442 */
443 clrbits_be32(&cp->cp_peso, 0x00031980);
444 }
445
iop_setup_miae(void)446 void iop_setup_miae(void)
447 {
448 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
449 iop8xx_t __iomem *iop = &immr->im_ioport;
450 cpm8xx_t __iomem *cp = &immr->im_cpm;
451
452 /* Wait reset on FPGA_F */
453 udelay(100);
454
455 /* Load CPM relocation code */
456 cpm_load_patch(cp);
457
458 /* Set the front panel LED color to red */
459 clrbits_8((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44, 0x02);
460
461 /* We must initialize data before changing direction */
462 setbits_be16(&iop->iop_pcdat, 0x0888);
463 setbits_be16(&iop->iop_pddat, 0x0201);
464 setbits_be32(&cp->cp_pbdat, 0x00021510);
465 setbits_be32(&cp->cp_pedat, 0x00000002);
466
467 /*
468 * PAPAR[13] = 1 [0x0004] -> GPIO: (RXD2)
469 * PAPAR[12] = 1 [0x0008] -> GPIO: (TXD2)
470 * PAPAR[9] = 1 [0x0040] -> GPIO: (TDM1O)
471 * PAPAR[8] = 1 [0x0080] -> GPIO: (TDM1I)
472 * PAPAR[7] = 1 [0x0100] -> GPIO: (TDM_BCLK_MPC)
473 * PAPAR[6] = 1 [0x0200] -> GPIO: (CLK2)
474 */
475 setbits_be16(&iop->iop_papar, 0x03CC);
476
477 /*
478 * PBODR[16] = 0 [0x00008000] -> GPIO: (L1ST4)
479 */
480 clrbits_be16(&cp->cp_pbodr, 0x00008000);
481
482 /*
483 * PBDIR[27] = 1 [0x00000010] -> GPIO: (WR_TEMP2)
484 * PBDIR[26] = 1 [0x00000020] -> GPIO: (BRG02)
485 * PBDIR[23] = 1 [0x00000100] -> GPIO: (CS_TEMP2)
486 * PBDIR[18] = 1 [0x00002000] -> GPIO: (RTS2)
487 * PBDIR[16] = 0 [0x00008000] -> GPIO: (L1ST4)
488 * PBDIR[15] = 1 [0x00010000] -> GPIO: (BRG03)
489 * PBDIR[14] = 1 [0x00020000] -> GPIO: (CS_TEMP)
490 */
491 clrsetbits_be32(&cp->cp_pbdir, 0x0003A130, 0x00032130);
492
493 /*
494 * PBPAR[20] = 1 [0x00000800] -> GPIO: (SMRXD2)
495 * PBPAR[17] = 1 [0x00004000] -> GPIO: (L1ST3)
496 * PBPAR[16] = 1 [0x00008000] -> GPIO: (L1ST4)
497 */
498 setbits_be32(&cp->cp_pbpar, 0x0000C800);
499
500 /*
501 * PCPAR[14] = 1 [0x0002] -> GPIO: (L1ST2)
502 */
503 setbits_be16(&iop->iop_pcpar, 0x0002);
504
505 /*
506 * PDPAR[14] = 1 [0x0002] -> GPIO: (TDM_FS_MPC)
507 * PDPAR[11] = 1 [0x0010] -> GPIO: (RXD3)
508 * PDPAR[10] = 1 [0x0020] -> GPIO: (TXD3)
509 * PDPAR[9] = 1 [0x0040] -> GPIO: (TXD4)
510 * PDPAR[7] = 1 [0x0100] -> GPIO: (RTS3)
511 * PDPAR[5] = 1 [0x0400] -> GPIO: (CLK8)
512 * PDPAR[3] = 1 [0x1000] -> GPIO: (CLK7)
513 */
514 setbits_be16(&iop->iop_pdpar, 0x1572);
515
516 /*
517 * PEPAR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
518 * PEPAR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
519 * PEPAR[25] = 1 [0x00000040] -> GPIO: (RXD4)
520 * PEPAR[24] = 1 [0x00000080] -> GPIO: (BRG01)
521 * PEPAR[23] = 1 [0x00000100] -> GPIO: (L1ST1)
522 * PEPAR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
523 * PEPAR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
524 * PEPAR[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
525 * PEPAR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
526 * PEPAR[17] = 1 [0x00004000] -> GPIO: (CLK5)
527 * PEPAR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
528 * PEPAR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
529 * PEPAR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
530 */
531 setbits_be32(&cp->cp_pepar, 0x0003DFF0);
532
533 /*
534 * PADIR[9] = 1 [0x0040] -> GPIO: (TDM1O)
535 * PADIR[8] = 1 [0x0080] -> GPIO: (TDM1I)
536 * PADIR[5] = 0 [0x0400] -> GPIO: ()
537 */
538 clrsetbits_be16(&iop->iop_padir, 0x04C0, 0x00C0);
539
540 /*
541 * PCDIR[15] = 1 [0x0001] -> GPIO: (WP_EEPROM2)
542 * PCDIR[14] = 1 [0x0002] -> GPIO: (L1ST2)
543 * PCDIR[13] = 0 [0x0004] -> GPIO: ()
544 * PCDIR[12] = 1 [0x0008] -> GPIO: (CS_EEPROM2)
545 * PCDIR[8] = 1 [0x0080] -> GPIO: (CS_CODEC_2)
546 * PCDIR[4] = 1 [0x0800] -> GPIO: (CS_CODEC_1)
547 */
548 clrsetbits_be16(&iop->iop_pcdir, 0x088F, 0x088B);
549
550 /*
551 * PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
552 * PDDIR[6] = 1 [0x0200] -> GPIO: (CS_CODEC_3)
553 */
554 setbits_be16(&iop->iop_pddir, 0x0240);
555
556 /*
557 * PEDIR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
558 * PEDIR[27] = 1 [0x00000010] -> GPIO: (R2_RXER)
559 * PEDIR[26] = 1 [0x00000020] -> GPIO: (R2_CRS_DV)
560 * PEDIR[23] = 1 [0x00000100] -> GPIO: (L1ST1)
561 * PEDIR[22] = 1 [0x00000200] -> GPIO: (R2_RXD1)
562 * PEDIR[21] = 1 [0x00000400] -> GPIO: (R2_RXD0)
563 * PEDIR[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
564 * PEDIR[18] = 1 [0x00002000] -> GPIO: (PE18)
565 * PEDIR[16] = 1 [0x00008000] -> GPIO: (R2_REF_CLK)
566 * PEDIR[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
567 * PEDIR[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
568 */
569 setbits_be32(&cp->cp_pedir, 0x0003B732);
570
571 /*
572 * PAODR[10] = 1 [0x0020] -> GPIO: (INIT_FPGA_F)
573 */
574 setbits_be16(&iop->iop_paodr, 0x0020);
575
576 /*
577 * PEODR[30] = 1 [0x00000002] -> GPIO: (FPGA_FIRMWARE)
578 * PEODR[18] = 0 [0x00002000] -> GPIO: (PE18)
579 */
580 clrsetbits_be32(&cp->cp_peodr, 0x00002002, 0x00000002);
581
582 /*
583 * PESO[24] = 1 [0x00000080] -> GPIO: (BRG01)
584 * PESO[23] = 1 [0x00000100] -> GPIO: (L1ST1)
585 * PESO[20] = 1 [0x00000800] -> GPIO: (SMTXD2)
586 * PESO[19] = 1 [0x00001000] -> GPIO: (R2_TXEN)
587 * PESO[15] = 1 [0x00010000] -> GPIO: (R2_TXD1)
588 * PESO[14] = 1 [0x00020000] -> GPIO: (R2_TXD0)
589 */
590 setbits_be32(&cp->cp_peso, 0x00031980);
591 }
592
593 /* Specific board initialization */
board_early_init_f(void)594 int board_early_init_f(void)
595 {
596 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
597 iop8xx_t __iomem *iop = &immr->im_ioport;
598 cpm8xx_t __iomem *cp = &immr->im_cpm;
599
600 /* MPC885 Port settings common to all boards */
601 setbits_be16(&iop->iop_padat, 0x0000);
602
603 /* Port A (MPC885 reference manual - 34.2) */
604 /*
605 * In/Out or per. Function 0/1
606 * PADIR[15] = 0 [0x0001] -> GPIO: (USB_RXD)
607 * PADIR[14] = 0 [0x0002] -> GPIO: (USB_OE)
608 * PADIR[13] = 0 [0x0004] -> GPIO: ()
609 * PADIR[12] = 0 [0x0008] -> GPIO: ()
610 * PADIR[11] = 1 [0x0010] -> GPIO: (R1_TXD0)
611 * PADIR[10] = 0 [0x0020] -> GPIO: ()
612 * PADIR[7] = 0 [0x0100] -> GPIO: ()
613 * PADIR[6] = 0 [0x0200] -> GPIO: ()
614 * PADIR[4] = 1 [0x0800] -> GPIO: (R1_TXD1)
615 * PADIR[3] = 0 [0x1000] -> GPIO: (R1_RXER)
616 * PADIR[2] = 0 [0x2000] -> GPIO: (R1_CRS_DV)
617 * PADIR[1] = 0 [0x4000] -> GPIO: (R1_RXD0)
618 * PADIR[0] = 0 [0x8000] -> GPIO: (R1_RXD1)
619 */
620 clrsetbits_be16(&iop->iop_padir, 0xFB3F, 0x0810);
621
622 /*
623 * Open drain or active output
624 * PAODR[15] = x [0x0001]
625 * PAODR[14] = 0 [0x0002]
626 * PAODR[13] = x [0x0004]
627 * PAODR[12] = 0 [0x0008]
628 * PAODR[11] = 0 [0x0010]
629 * PAODR[9] = 0 [0x0040]
630 * PAODR[8] = 0 [0x0080]
631 * PAODR[7] = 0 [0x0100]
632 */
633 clrbits_be16(&iop->iop_paodr, 0x01DF);
634
635 /*
636 * GPIO or per. Function
637 * PAPAR[15] = 1 [0x0001] -> GPIO: (USB_RXD)
638 * PAPAR[14] = 1 [0x0002] -> GPIO: (USB_OE)
639 * PAPAR[11] = 1 [0x0010] -> GPIO: (R1_TXD0)
640 * PAPAR[10] = 0 [0x0020] -> GPIO: (INIT_FPGA_F)
641 * PAPAR[5] = 0 [0x0400] -> GPIO: ()
642 * PAPAR[4] = 1 [0x0800] -> GPIO: (R1_TXD1)
643 * PAPAR[3] = 1 [0x1000] -> GPIO: (R1_RXER)
644 * PAPAR[2] = 1 [0x2000] -> GPIO: (R1_CRS_DV)
645 * PAPAR[1] = 1 [0x4000] -> GPIO: (R1_RXD0)
646 * PAPAR[0] = 1 [0x8000] -> GPIO: (R1_RXD1)
647 */
648 clrsetbits_be16(&iop->iop_papar, 0xFC33, 0xF813);
649
650 /* Port B (MPC885 reference manual - 34.3) */
651 /*
652 * In/Out or per. Function 0/1
653 * PBDIR[31] = 0 [0x00000001] -> GPIO: (R1_REF_CLK)
654 * PBDIR[30] = 1 [0x00000002] -> GPIO: (CLK)
655 * PBDIR[29] = 1 [0x00000004] -> GPIO: (MOSI)
656 * PBDIR[28] = 1 [0x00000008] -> GPIO: (MISO)
657 * PBDIR[25] = 0 [0x00000040] -> GPIO: (SMTXD1)
658 * PBDIR[24] = 0 [0x00000080] -> GPIO: (SMRXD1)
659 * PBDIR[22] = 0 [0x00000200] -> GPIO: (INIT_FPGA_MEZZ)
660 * PBDIR[21] = 1 [0x00000400] -> GPIO: (CS_EEPROM)
661 * PBDIR[20] = 0 [0x00000800] -> GPIO: (SMRXD2)
662 * PBDIR[19] = 1 [0x00001000] -> GPIO: (WR_TEMP)
663 * PBDIR[17] = 0 [0x00004000] -> GPIO: (DONE_FPGA_MEZZ)
664 */
665 clrsetbits_be32(&cp->cp_pbdir, 0x00005ECF, 0x0000140E);
666
667 /*
668 * Open drain or active output
669 * PBODR[31] = 0 [0x00000001] -> GPIO: (R1_REF_CLK)
670 * PBODR[30] = 0 [0x00000002] -> GPIO: (CLK)
671 * PBODR[29] = 0 [0x00000004] -> GPIO: (MOSI)
672 * PBODR[28] = 0 [0x00000008] -> GPIO: (MISO)
673 * PBODR[27] = 0 [0x00000010] -> GPIO: (WR_TEMP2)
674 * PBODR[26] = 0 [0x00000020] -> GPIO: (BRG02)
675 * PBODR[25] = 0 [0x00000040] -> GPIO: (SMTXD1)
676 * PBODR[24] = 0 [0x00000080] -> GPIO: (SMRXD1)
677 * PBODR[23] = 0 [0x00000100] -> GPIO: (CS_TEMP2)
678 * PBODR[22] = 0 [0x00000200] -> GPIO: (INIT_FPGA_MEZZ)
679 * PBODR[21] = 0 [0x00000400] -> GPIO: (CS_EEPROM)
680 * PBODR[20] = 0 [0x00000800] -> GPIO: (SMRXD2)
681 * PBODR[19] = 0 [0x00001000] -> GPIO: (WR_TEMP)
682 * PBODR[18] = 0 [0x00002000] -> GPIO: (RTS2)
683 * PBODR[17] = 0 [0x00004000] -> GPIO: (DONE_FPGA_MEZZ)
684 */
685 clrbits_be16(&cp->cp_pbodr, 0x00007FFF);
686
687 /*
688 * GPIO or per. Function
689 * PBPAR[31] = 1 [0x00000001] -> GPIO: (R1_REF_CLK)
690 * PBPAR[30] = 1 [0x00000002] -> GPIO: (CLK)
691 * PBPAR[29] = 1 [0x00000004] -> GPIO: (MOSI)
692 * PBPAR[28] = 1 [0x00000008] -> GPIO: (MISO)
693 * PBPAR[27] = 0 [0x00000010] -> GPIO: (WR_TEMP2)
694 * PBPAR[26] = 0 [0x00000020] -> GPIO: (BRG02)
695 * PBPAR[25] = 1 [0x00000040] -> GPIO: (SMTXD1)
696 * PBPAR[24] = 1 [0x00000080] -> GPIO: (SMRXD1)
697 * PBPAR[23] = 0 [0x00000100] -> GPIO: (CS_TEMP2)
698 * PBPAR[22] = 0 [0x00000200] -> GPIO: (INIT_FPGA_MEZZ)
699 * PBPAR[21] = 0 [0x00000400] -> GPIO: (CS_EEPROM)
700 * PBPAR[19] = 0 [0x00001000] -> GPIO: (WR_TEMP)
701 * PBPAR[18] = 0 [0x00002000] -> GPIO: (RTS2)
702 * PBPAR[15] = 0 [0x00010000] -> GPIO: (BRG03)
703 * PBPAR[14] = 0 [0x00020000] -> GPIO: (CS_TEMP)
704 */
705 clrsetbits_be32(&cp->cp_pbpar, 0x000337FF, 0x000000CF);
706
707 /* Port C (MPC885 Reference Manual - 34.4) */
708 /*
709 * In/Out or per. Function 0/1
710 * PCDIR[11] = 0 [0x0010] -> GPIO: (USB_RXP)
711 * PCDIR[10] = 0 [0x0020] -> GPIO: (USB_RXN)
712 * PCDIR[9] = 0 [0x0040] -> GPIO: (CTS2)
713 * PCDIR[7] = 1 [0x0100] -> GPIO: (USB_TXP)
714 * PCDIR[6] = 1 [0x0200] -> GPIO: (USB_TXN)
715 * PCDIR[5] = 0 [0x0400] -> GPIO: (CTS3)
716 */
717 clrsetbits_be16(&iop->iop_pcdir, 0x0770, 0x0300);
718
719 /*
720 * GPIO or per. Function
721 * PCPAR[15] = 0 [0x0001] -> GPIO: (WP_EEPROM2)
722 * PCPAR[13] = 0 [0x0004] -> GPIO: (CS_POT1)
723 * PCPAR[12] = 0 [0x0008] -> GPIO: (CS_EEPROM2)
724 * PCPAR[11] = 0 [0x0010] -> GPIO: (USB_RXP)
725 * PCPAR[10] = 0 [0x0020] -> GPIO: (USB_RXN)
726 * PCPAR[9] = 0 [0x0040] -> GPIO: (CTS2)
727 * PCPAR[8] = 0 [0x0080] -> GPIO: (CS_CODEC_FAV)
728 * PCPAR[7] = 1 [0x0100] -> GPIO: (USB_TXP)
729 * PCPAR[6] = 1 [0x0200] -> GPIO: (USB_TXN)
730 * PCPAR[5] = 0 [0x0400] -> GPIO: (CTS3)
731 * PCPAR[4] = 0 [0x0800] -> GPIO: (CS_CODEC_RADIO)
732 */
733 clrsetbits_be16(&iop->iop_pcpar, 0x0FFD, 0x0300);
734
735 /*
736 * Special Option register
737 * PCSO[15] = 0 [0x0001] -> GPIO: (WP_EEPROM2)
738 * PCSO[14] = 0 [0x0002] -> GPIO: (CS_POT2)
739 * PCSO[13] = x [0x0004] -> Reserved
740 * PCSO[12] = x [0x0008] -> Reserved
741 * PCSO[11] = 1 [0x0010] -> GPIO: (USB_RXP)
742 * PCSO[10] = 1 [0x0020] -> GPIO: (USB_RXN)
743 * PCSO[9] = 1 [0x0040] -> GPIO: (CTS2)
744 * PCSO[8] = 0 [0x0080] -> GPIO: (CS_CODEC_FAV)
745 * PCSO[7] = 0 [0x0100] -> GPIO: (USB_TXP)
746 * PCSO[6] = 0 [0x0200] -> GPIO: (USB_TXN)
747 * PCSO[5] = 1 [0x0400] -> GPIO: (CTS3)
748 * PCSO[4] = 0 [0x0800] -> GPIO: (CS_CODEC_RADIO)
749 */
750 clrsetbits_be16(&iop->iop_pcso, 0x0FF3, 0x0470);
751
752 /*
753 * Interrupt or IO
754 * PCINT[15] = 0 [0x0001] -> GPIO: ()
755 * PCINT[14] = 0 [0x0002] -> GPIO: ()
756 * PCINT[13] = 0 [0x0004] -> GPIO: ()
757 * PCINT[12] = 0 [0x0008] -> GPIO: ()
758 * PCINT[11] = 0 [0x0010] -> GPIO: (USB_RXP)
759 * PCINT[10] = 0 [0x0020] -> GPIO: (USB_RXN)
760 * PCINT[9] = 0 [0x0040] -> GPIO: ()
761 * PCINT[8] = 0 [0x0080] -> GPIO: ()
762 * PCINT[7] = 0 [0x0100] -> GPIO: (USB_TXP)
763 * PCINT[6] = 0 [0x0200] -> GPIO: (USB_TXN)
764 * PCINT[5] = 0 [0x0400] -> GPIO: ()
765 * PCINT[4] = 0 [0x0800] -> GPIO: ()
766 */
767 clrbits_be16(&iop->iop_pcint, 0x0FFF);
768
769 /* Port D (MPC885 Reference Manual - 34.5) */
770 /*
771 * In/Out or per. Function 0/1
772 * PDDIR[15] = 1 [0x0001] -> GPIO: (CS_NAND)
773 * PDDIR[14] = 0 [0x0002] -> GPIO: (TDM_FS_MPC)
774 * PDDIR[13] = 1 [0x0004] -> GPIO: (ALE_NAND)
775 * PDDIR[12] = 1 [0x0008] -> GPIO: (CLE_NAND)
776 * PDDIR[11] = 0 [0x0010] -> GPIO: (RXD3)
777 * PDDIR[10] = 0 [0x0020] -> GPIO: (TXD3)
778 * PDDIR[9] = 1 [0x0040] -> GPIO: (TXD4)
779 * PDDIR[8] = 0 [0x0080] -> GPIO: (R_MDC)
780 * PDDIR[7] = 0 [0x0100] -> GPIO: (RTS3)
781 * PDDIR[5] = 0 [0x0400] -> GPIO: (CLK8)
782 * PDDIR[4] = 0 [0x0800] -> GPIO: (CLK4)
783 * PDDIR[3] = 0 [0x1000] -> GPIO: (CLK7)
784 */
785 clrsetbits_be16(&iop->iop_pddir, 0x1DFF, 0x004D);
786
787 /*
788 * GPIO or per. Function
789 * PDPAR[15] = 0 [0x0001] -> GPIO: (CS_NAND)
790 * PDPAR[13] = 0 [0x0004] -> GPIO: (ALE_NAND)
791 * PDPAR[12] = 0 [0x0008] -> GPIO: (CLE_NAND)
792 * PDPAR[8] = 1 [0x0080] -> GPIO: (R_MDC)
793 * PDPAR[6] = 0 [0x0200] -> GPIO: (INIT_FPGA_RADIO)
794 * PDPAR[4] = 1 [0x0800] -> GPIO: (CLK4)
795 */
796 clrsetbits_be16(&iop->iop_pdpar, 0x0A8D, 0x0880);
797
798 /* Port E (MPC885 Reference Manual - 34.6) */
799 /*
800 * In/Out or per. Function 0/1
801 * PEDIR[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
802 * PEDIR[29] = 1 [0x00000004] -> GPIO: (USB_SPEED)
803 * PEDIR[28] = 1 [0x00000008] -> GPIO: (USB_SUSPEND)
804 * PEDIR[25] = 0 [0x00000040] -> GPIO: (RXD4)
805 * PEDIR[24] = 0 [0x00000080] -> GPIO: (BRG01)
806 * PEDIR[20] = 0 [0x00000800] -> GPIO: (SMTXD2)
807 * PEDIR[17] = 0 [0x00004000] -> GPIO: (CLK5)
808 */
809 clrsetbits_be32(&cp->cp_pedir, 0x000048CD, 0x0000000C);
810
811 /*
812 * open drain or active output
813 * PEODR[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
814 * PEODR[29] = 0 [0x00000004] -> GPIO: (USB_SPEED)
815 * PEODR[28] = 1 [0x00000008] -> GPIO: (USB_SUSPEND)
816 * PEODR[27] = 0 [0x00000010] -> GPIO: (R2_RXER)
817 * PEODR[26] = 0 [0x00000020] -> GPIO: (R2_CRS_DV)
818 * PEODR[25] = 0 [0x00000040] -> GPIO: (RXD4)
819 * PEODR[24] = 0 [0x00000080] -> GPIO: (BRG01)
820 * PEODR[23] = 0 [0x00000100] -> GPIO: (DONE_FPGA_RADIO)
821 * PEODR[22] = 0 [0x00000200] -> GPIO: (R2_RXD1)
822 * PEODR[21] = 0 [0x00000400] -> GPIO: (R2_RXD0)
823 * PEODR[20] = 0 [0x00000800] -> GPIO: (SMTXD2)
824 * PEODR[19] = 0 [0x00001000] -> GPIO: (R2_TXEN)
825 * PEODR[17] = 0 [0x00004000] -> GPIO: (CLK5)
826 * PEODR[16] = 0 [0x00008000] -> GPIO: (R2_REF_CLK)
827 */
828 clrsetbits_be32(&cp->cp_peodr, 0x0000DFFD, 0x00000008);
829
830 /*
831 * GPIO or per. Function
832 * PEPAR[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
833 * PEPAR[30] = 0 [0x00000002] -> GPIO: (PROG_FPGA_FIRMWARE)
834 * PEPAR[29] = 0 [0x00000004] -> GPIO: (USB_SPEED)
835 * PEPAR[28] = 0 [0x00000008] -> GPIO: (USB_SUSPEND)
836 * PEPAR[18] = 0 [0x00002000] -> GPIO: (PROG_FPGA_RADIO)
837 */
838 clrbits_be32(&cp->cp_pepar, 0x0000200F);
839
840 /*
841 * Special Option register
842 * PESO[31] = 0 [0x00000001] -> GPIO: (DONE_FPGA_FIRMWARE)
843 * PESO[30] = 0 [0x00000002] -> GPIO: (PROG_FPGA_FIRMWARE)
844 * PESO[29] = 0 [0x00000004] -> GPIO: (USB_SPEED)
845 * PESO[28] = 0 [0x00000008] -> GPIO: (USB_SUSPEND)
846 * PESO[27] = 0 [0x00000010] -> GPIO: (R2_RXER)
847 * PESO[26] = 0 [0x00000020] -> GPIO: (R2_CRS_DV)
848 * PESO[25] = 0 [0x00000040] -> GPIO: (RXD4)
849 * PESO[22] = 0 [0x00000200] -> GPIO: (R2_RXD1)
850 * PESO[21] = 0 [0x00000400] -> GPIO: (R2_RXD0)
851 * PESO[18] = 0 [0x00002000] -> GPIO: (PROG_FPGA_RADIO)
852 * PESO[17] = 0 [0x00004000] -> GPIO: (CLK5)
853 * PESO[16] = 0 [0x00008000] -> GPIO: (R2_REF_CLK)
854 */
855 clrbits_be32(&cp->cp_peso, 0x0000E67F);
856
857 /* Is a motherboard present ? */
858 if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) {
859 /* Initialize signal PROG_FPGA_FIRMWARE */
860 out_be32(&cp->cp_pedat, 0x00000002);
861 out_be32(&cp->cp_peodr, 0x00000002);
862 out_be32(&cp->cp_pedir, 0x00000002);
863
864 /* Check if fpga firmware is loaded */
865 if (!(in_be32(&cp->cp_pedat) & 0x00000001)) {
866 /* Load fpga firmware */
867 /* Activate PROG_FPGA_FIRMWARE for 1 usec */
868 clrbits_be32(&cp->cp_pedat, 0x00000002);
869 udelay(1);
870 setbits_be32(&cp->cp_pedat, 0x00000002);
871
872 /* Wait 200 msec and check DONE_FPGA_FIRMWARE */
873 mdelay(200);
874 if (!(in_be32(&cp->cp_pedat) & 0x00000001))
875 hang();
876
877 /* Send a reset signal and wait for 20 msec */
878 clrbits_be16(ADDR_CPLD_R_RESET, R_RST_STATUS);
879 mdelay(20);
880 setbits_be16(ADDR_CPLD_R_RESET, R_RST_STATUS);
881 }
882
883 /* Wait 300 msec and check the reset state */
884 mdelay(300);
885 if (!(in_be16(ADDR_CPLD_R_RESET) & R_RESET_STATUS))
886 hang();
887
888 iop_setup_common();
889 } else {
890 iop_setup_cmpc885();
891 }
892
893 return 0;
894 }
895