1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <image.h>
9 #include <init.h>
10 #include <spl.h>
11
12 #include <asm-generic/gpio.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/ddr.h>
15 #include <asm/arch/imx8mp_pins.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/io.h>
18 #include <asm/mach-imx/boot_mode.h>
19
20 #include <dm/uclass.h>
21 #include <dm/device.h>
22 #include <dm/uclass-internal.h>
23 #include <dm/device-internal.h>
24
25 #include <power/pmic.h>
26 #include <power/pca9450.h>
27
28 #include "lpddr4_timing.h"
29
30 #include "../common/common.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
data_modul_imx_edm_sbc_board_power_init(void)34 int data_modul_imx_edm_sbc_board_power_init(void)
35 {
36 struct udevice *dev;
37 int ret;
38
39 ret = pmic_get("pmic@25", &dev);
40 if (ret == -ENODEV) {
41 puts("Failed to get PMIC\n");
42 return 0;
43 }
44 if (ret != 0)
45 return ret;
46
47 /* BUCKxOUT_DVS0/1 control BUCK123 output. */
48 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
49
50 /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
51 if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
52 /* Set DVS0 to 0.85V for special case. */
53 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
54 else
55 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
56
57 /* Set DVS1 to 0.85v for suspend. */
58 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
59
60 /*
61 * Enable DVS control through PMIC_STBY_REQ and
62 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
63 */
64 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
65
66 /* Kernel uses OD/OD frequency for SoC. */
67
68 /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
69 pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
70
71 /* Set LDO4 and CONFIG2 to enable the I2C level translator. */
72 pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
73 pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
74
75 return 0;
76 }
77
spl_board_boot_device(enum boot_device boot_dev_spl)78 int spl_board_boot_device(enum boot_device boot_dev_spl)
79 {
80 if (boot_dev_spl == SPI_NOR_BOOT) /* SPI NOR */
81 return BOOT_DEVICE_SPI;
82
83 if (boot_dev_spl == MMC3_BOOT) /* eMMC */
84 return BOOT_DEVICE_MMC2;
85
86 return BOOT_DEVICE_MMC1; /* SD */
87 }
88
board_boot_order(u32 * spl_boot_list)89 void board_boot_order(u32 *spl_boot_list)
90 {
91 int boot_device = spl_boot_device();
92
93 spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC 8:SPI NOR */
94
95 if (boot_device == BOOT_DEVICE_SPI) { /* SPI, eMMC, SD */
96 spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
97 spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */
98 } else if (boot_device == BOOT_DEVICE_MMC1) { /* SD, eMMC, SPI */
99 spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
100 spl_boot_list[2] = BOOT_DEVICE_SPI; /* SPI */
101 } else { /* eMMC, SPI, SD */
102 spl_boot_list[1] = BOOT_DEVICE_SPI; /* SPI */
103 spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */
104 }
105
106 spl_boot_list[3] = BOOT_DEVICE_UART; /* YModem */
107 spl_boot_list[4] = BOOT_DEVICE_NONE;
108 }
109
110 static struct dram_timing_info *dram_timing_info[8] = {
111 &dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */
112 NULL, /* 32 Gbit x16 */
113 NULL, /* 16 Gbit x32 */
114 NULL, /* 16 Gbit x16 */
115 NULL, /* 8 Gbit x32 */
116 NULL, /* 8 Gbit x16 */
117 NULL, /* INVALID */
118 NULL, /* INVALID */
119 };
120
board_init_f(ulong dummy)121 void board_init_f(ulong dummy)
122 {
123 dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info);
124 }
125