1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Amarula Solutions(India)
4 * Copyright (C) 2016 Engicam S.r.l.
5 *
6 * Authors:
7 * Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
8 * Jagan Teki <jagan@amarulasolutions.com>
9 */
10
11 #include <common.h>
12 #include <hang.h>
13 #include <init.h>
14 #include <log.h>
15 #include <spl.h>
16 #include <asm/global_data.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx8mp_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/gpio.h>
22 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <asm/arch/ddr.h>
25 #include <power/pmic.h>
26 #include <power/pca9450.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
spl_board_boot_device(enum boot_device boot_dev_spl)30 int spl_board_boot_device(enum boot_device boot_dev_spl)
31 {
32 return BOOT_DEVICE_BOOTROM;
33 }
34
spl_dram_init(void)35 void spl_dram_init(void)
36 {
37 ddr_init(&dram_timing);
38 }
39
40 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
41 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
42 struct i2c_pads_info i2c_pad_info1 = {
43 .scl = {
44 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
45 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
46 .gp = IMX_GPIO_NR(5, 14),
47 },
48 .sda = {
49 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
50 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
51 .gp = IMX_GPIO_NR(5, 15),
52 },
53 };
54
55 #if CONFIG_IS_ENABLED(POWER_LEGACY)
56 #define I2C_PMIC 0
power_init_board(void)57 int power_init_board(void)
58 {
59 struct pmic *p;
60 int ret;
61
62 ret = power_pca9450_init(I2C_PMIC, 0x25);
63 if (ret)
64 printf("power init failed");
65 p = pmic_get("PCA9450");
66 pmic_probe(p);
67
68 /* BUCKxOUT_DVS0/1 control BUCK123 output */
69 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
70
71 #ifdef CONFIG_IMX8M_LPDDR4
72 /*
73 * increase VDD_SOC to typical value 0.95V before first
74 * DRAM access, set DVS1 to 0.85v for suspend.
75 * Enable DVS control through PMIC_STBY_REQ and
76 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
77 */
78 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
79 /* set DVS0 to 0.85v for special case*/
80 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
81 #else
82 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
83 #endif
84 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
85 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
86
87 /* Kernel uses OD/OD freq for SOC */
88 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
89 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
90 #elif defined(CONFIG_IMX8M_DDR4)
91 /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
92 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
93
94 /* Set NVCC_DRAM to 1.2v for DDR4 */
95 pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
96 #endif
97
98 return 0;
99 }
100 #endif
101
spl_board_init(void)102 void spl_board_init(void)
103 {
104 /* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it.
105 * Should set the clock after PMIC setting done.
106 * Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC
107 */
108 clock_enable(CCGR_GIC, 0);
109 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
110 clock_enable(CCGR_GIC, 1);
111
112 puts("Normal Boot\n");
113 }
114
115 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)116 int board_fit_config_name_match(const char *name)
117 {
118 /* Just empty function now - can't decide what to choose */
119 debug("%s: %s\n", __func__, name);
120
121 return 0;
122 }
123 #endif
124
board_init_f(ulong dummy)125 void board_init_f(ulong dummy)
126 {
127 int ret;
128
129 arch_cpu_init();
130
131 init_uart_clk(1);
132
133 ret = spl_early_init();
134 if (ret) {
135 debug("spl_early_init() failed: %d\n", ret);
136 hang();
137 }
138
139 preloader_console_init();
140
141 enable_tzc380();
142
143 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
144
145 power_init_board();
146
147 /* DDR initialization */
148 spl_dram_init();
149 }
150