1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2009-2015
8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
9 * esd electronic system design gmbh <www.esd.eu>
10 */
11
12 #include <common.h>
13 #include <env.h>
14 #include <init.h>
15 #include <net.h>
16 #include <serial.h>
17 #include <vsprintf.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20 #include <asm/gpio.h>
21 #include <asm/mach-types.h>
22 #include <asm/setup.h>
23 #include <asm/arch/at91sam9_smc.h>
24 #include <asm/arch/at91_common.h>
25 #include <asm/arch/at91_pmc.h>
26 #include <asm/arch/at91_rstc.h>
27 #include <asm/arch/at91_matrix.h>
28 #include <asm/arch/at91_pio.h>
29 #include <asm/arch/clk.h>
30 #include <netdev.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 /*
35 * Miscelaneous platform dependent initialisations
36 */
37
38 #ifdef CONFIG_REVISION_TAG
39 static int hw_rev = -1; /* hardware revision */
40
get_hw_rev(void)41 int get_hw_rev(void)
42 {
43 if (hw_rev >= 0)
44 return hw_rev;
45
46 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
47 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
48 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
49 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
50
51 if (hw_rev == 15)
52 hw_rev = 0;
53
54 return hw_rev;
55 }
56 #endif /* CONFIG_REVISION_TAG */
57
58 #ifdef CONFIG_CMD_NAND
meesc_nand_hw_init(void)59 static void meesc_nand_hw_init(void)
60 {
61 unsigned long csa;
62 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
63 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
64
65 /* Enable CS3 */
66 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
67 writel(csa, &matrix->csa[0]);
68
69 /* Configure SMC CS3 for NAND/SmartMedia */
70 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
71 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
72 &smc->cs[3].setup);
73
74 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
75 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
76 &smc->cs[3].pulse);
77
78 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
79 &smc->cs[3].cycle);
80 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
81 AT91_SMC_MODE_EXNW_DISABLE |
82 AT91_SMC_MODE_DBW_8 |
83 AT91_SMC_MODE_TDF_CYCLE(12),
84 &smc->cs[3].mode);
85
86 /* Configure RDY/BSY */
87 gpio_direction_input(CFG_SYS_NAND_READY_PIN);
88
89 /* Enable NandFlash */
90 gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
91 }
92 #endif /* CONFIG_CMD_NAND */
93
94 #ifdef CONFIG_MACB
meesc_macb_hw_init(void)95 static void meesc_macb_hw_init(void)
96 {
97 at91_periph_clk_enable(ATMEL_ID_EMAC);
98
99 at91_macb_hw_init();
100 }
101 #endif
102
103 /*
104 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
105 * controller debugging
106 * The ET1100 is located at physical address 0x70000000
107 * Its process memory is located at physical address 0x70001000
108 */
meesc_ethercat_hw_init(void)109 static void meesc_ethercat_hw_init(void)
110 {
111 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
112
113 /* Configure SMC EBI1_CS0 for EtherCAT */
114 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
115 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
116 &smc1->cs[0].setup);
117 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
118 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
119 &smc1->cs[0].pulse);
120 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
121 &smc1->cs[0].cycle);
122 /*
123 * Configure behavior at external wait signal, byte-select mode, 16 bit
124 * data bus width, none data float wait states and TDF optimization
125 */
126 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
127 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
128 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
129
130 /* Configure RDY/BSY */
131 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
132 }
133
dram_init(void)134 int dram_init(void)
135 {
136 /* dram_init must store complete ramsize in gd->ram_size */
137 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
138 PHYS_SDRAM_SIZE);
139 return 0;
140 }
141
dram_init_banksize(void)142 int dram_init_banksize(void)
143 {
144 gd->bd->bi_dram[0].start = PHYS_SDRAM;
145 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
146
147 return 0;
148 }
149
board_eth_init(struct bd_info * bis)150 int board_eth_init(struct bd_info *bis)
151 {
152 int rc = 0;
153 #ifdef CONFIG_MACB
154 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
155 #endif
156 return rc;
157 }
158
159 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)160 int checkboard(void)
161 {
162 char str[32];
163 u_char hw_type; /* hardware type */
164
165 /* read the "Type" register of the ET1100 controller */
166 hw_type = readb(CFG_ET1100_BASE);
167
168 switch (hw_type) {
169 case 0x11:
170 case 0x3F:
171 /* ET1100 present, arch number of MEESC-Board */
172 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
173 puts("Board: CAN-EtherCAT Gateway");
174 break;
175 case 0xFF:
176 /* no ET1100 present, arch number of EtherCAN/2-Board */
177 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
178 puts("Board: EtherCAN/2 Gateway");
179 /* switch on LED1D */
180 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
181 break;
182 default:
183 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
184 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
185 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
186 puts("Board: EtherCAN/2 Gateway");
187 break;
188 }
189 if (env_get_f("serial#", str, sizeof(str)) > 0) {
190 puts(", serial# ");
191 puts(str);
192 }
193 #ifdef CONFIG_REVISION_TAG
194 printf("\nHardware-revision: 1.%d\n", get_hw_rev());
195 #endif
196 printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
197 return 0;
198 }
199 #endif /* CONFIG_DISPLAY_BOARDINFO */
200
201 #ifdef CONFIG_SERIAL_TAG
get_board_serial(struct tag_serialnr * serialnr)202 void get_board_serial(struct tag_serialnr *serialnr)
203 {
204 char *str;
205
206 char *serial = env_get("serial#");
207 if (serial) {
208 str = strchr(serial, '_');
209 if (str && (strlen(str) >= 4)) {
210 serialnr->high = (*(str + 1) << 8) | *(str + 2);
211 serialnr->low = hextoul(str + 3, NULL);
212 }
213 } else {
214 serialnr->high = 0;
215 serialnr->low = 0;
216 }
217 }
218 #endif
219
220 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)221 u32 get_board_rev(void)
222 {
223 return hw_rev | 0x100;
224 }
225 #endif
226
227 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)228 int misc_init_r(void)
229 {
230 char *str;
231 char buf[32];
232 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
233
234 /*
235 * Normally the processor clock has a divisor of 2.
236 * In some cases this this needs to be set to 4.
237 * Check the user has set environment mdiv to 4 to change the divisor.
238 */
239 str = env_get("mdiv");
240 if (str && (strcmp(str, "4") == 0)) {
241 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
242 AT91SAM9_PMC_MDIV_4, &pmc->mckr);
243 at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
244 serial_setbrg();
245 /* Notify the user that the clock is not default */
246 printf("Setting master clock to %s MHz\n",
247 strmhz(buf, get_mck_clk_rate()));
248 }
249
250 return 0;
251 }
252 #endif /* CONFIG_MISC_INIT_R */
253
board_early_init_f(void)254 int board_early_init_f(void)
255 {
256 at91_periph_clk_enable(ATMEL_ID_UHP);
257
258 return 0;
259 }
260
board_init(void)261 int board_init(void)
262 {
263 /* initialize ET1100 Controller */
264 meesc_ethercat_hw_init();
265
266 /* adress of boot parameters */
267 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
268
269 #ifdef CONFIG_CMD_NAND
270 meesc_nand_hw_init();
271 #endif
272 #ifdef CONFIG_MACB
273 meesc_macb_hw_init();
274 #endif
275 #ifdef CONFIG_AT91_CAN
276 at91_can_hw_init();
277 #endif
278 #ifdef CONFIG_USB_OHCI_NEW
279 at91_uhp_hw_init();
280 #endif
281 return 0;
282 }
283