1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019, 2021 NXP
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <cpu_func.h>
9 #include <hang.h>
10 #include <image.h>
11 #include <init.h>
12 #include <log.h>
13 #include <spl.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx8mm_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/arch/ddr.h>
22
23 #include <dm/uclass.h>
24 #include <dm/device.h>
25 #include <dm/uclass-internal.h>
26 #include <dm/device-internal.h>
27
28 #include <power/pmic.h>
29 #include <power/pca9450.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
spl_board_boot_device(enum boot_device boot_dev_spl)33 int spl_board_boot_device(enum boot_device boot_dev_spl)
34 {
35 switch (boot_dev_spl) {
36 case USB_BOOT:
37 return BOOT_DEVICE_BOARD;
38 case SD2_BOOT:
39 case MMC2_BOOT:
40 return BOOT_DEVICE_MMC1;
41 case SD3_BOOT:
42 case MMC3_BOOT:
43 return BOOT_DEVICE_MMC2;
44 case QSPI_BOOT:
45 return BOOT_DEVICE_NOR;
46 default:
47 return BOOT_DEVICE_NONE;
48 }
49 }
50
spl_dram_init(void)51 static void spl_dram_init(void)
52 {
53 ddr_init(&dram_timing);
54 }
55
spl_board_init(void)56 void spl_board_init(void)
57 {
58 arch_misc_init();
59 }
60
61 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)62 int board_fit_config_name_match(const char *name)
63 {
64 /* Just empty function now - can't decide what to choose */
65 debug("%s: %s\n", __func__, name);
66
67 return 0;
68 }
69 #endif
70
power_init_board(void)71 static int power_init_board(void)
72 {
73 struct udevice *dev;
74 int ret;
75
76 ret = pmic_get("pca9450@25", &dev);
77 if (ret == -ENODEV) {
78 puts("No pmic\n");
79 return 0;
80 }
81 if (ret != 0)
82 return ret;
83
84 /* BUCKxOUT_DVS0/1 control BUCK123 output */
85 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
86
87 /* Buck 1 DVS control through PMIC_STBY_REQ */
88 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
89
90 /* Set DVS1 to 0.8v for suspend */
91 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
92
93 /* increase VDD_DRAM to 0.95v for 3Ghz DDR */
94 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
95
96 /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
97 pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
98
99 /* set VDD_SNVS_0V8 from default 0.85V */
100 pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
101
102 return 0;
103 }
104
board_init_f(ulong dummy)105 void board_init_f(ulong dummy)
106 {
107 struct udevice *dev;
108 int ret;
109
110 arch_cpu_init();
111
112 init_uart_clk(1);
113
114 timer_init();
115
116 /* Clear the BSS. */
117 memset(__bss_start, 0, __bss_end - __bss_start);
118
119 ret = spl_early_init();
120 if (ret) {
121 debug("spl_early_init() failed: %d\n", ret);
122 hang();
123 }
124
125 ret = uclass_get_device_by_name(UCLASS_CLK,
126 "clock-controller@30380000",
127 &dev);
128 if (ret < 0) {
129 printf("Failed to find clock node. Check device tree\n");
130 hang();
131 }
132
133 preloader_console_init();
134
135 enable_tzc380();
136
137 power_init_board();
138
139 /* DDR initialization */
140 spl_dram_init();
141
142 board_init_r(NULL, 0);
143 }
144