1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2018-2019, 2021 NXP
4 *
5 */
6
7 #include <common.h>
8 #include <hang.h>
9 #include <init.h>
10 #include <log.h>
11 #include <spl.h>
12 #include <asm/global_data.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/imx8mp_pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <asm/arch/ddr.h>
21 #include <power/pmic.h>
22 #include <power/pca9450.h>
23 #include <dm/uclass.h>
24 #include <dm/device.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
spl_board_boot_device(enum boot_device boot_dev_spl)28 int spl_board_boot_device(enum boot_device boot_dev_spl)
29 {
30 return BOOT_DEVICE_BOOTROM;
31 }
32
spl_dram_init(void)33 void spl_dram_init(void)
34 {
35 ddr_init(&dram_timing);
36 }
37
spl_board_init(void)38 void spl_board_init(void)
39 {
40 arch_misc_init();
41
42 /*
43 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
44 * not allow to change it. Should set the clock after PMIC
45 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
46 * set by ROM for ND VDD_SOC
47 */
48 clock_enable(CCGR_GIC, 0);
49 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
50 clock_enable(CCGR_GIC, 1);
51
52 puts("Normal Boot\n");
53 }
54
55 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
56 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
57 struct i2c_pads_info i2c_pad_info1 = {
58 .scl = {
59 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
60 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
61 .gp = IMX_GPIO_NR(5, 14),
62 },
63 .sda = {
64 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
65 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
66 .gp = IMX_GPIO_NR(5, 15),
67 },
68 };
69
70 #if CONFIG_IS_ENABLED(POWER_LEGACY)
71 #define I2C_PMIC 0
power_init_board(void)72 int power_init_board(void)
73 {
74 struct pmic *p;
75 int ret;
76
77 ret = power_pca9450_init(I2C_PMIC, 0x25);
78 if (ret)
79 printf("power init failed");
80 p = pmic_get("PCA9450");
81 pmic_probe(p);
82
83 /* BUCKxOUT_DVS0/1 control BUCK123 output */
84 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
85
86 /*
87 * increase VDD_SOC to typical value 0.95V before first
88 * DRAM access, set DVS1 to 0.85v for suspend.
89 * Enable DVS control through PMIC_STBY_REQ and
90 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
91 */
92 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
93 /* set DVS0 to 0.85v for special case*/
94 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
95 #else
96 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
97 #endif
98 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
99 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
100
101 /* Kernel uses OD/OD freq for SOC */
102 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
103 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
104
105 return 0;
106 }
107 #endif
108
109 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)110 int board_fit_config_name_match(const char *name)
111 {
112 /* Just empty function now - can't decide what to choose */
113 debug("%s: %s\n", __func__, name);
114
115 return 0;
116 }
117 #endif
118
119 /* Do not use BSS area in this phase */
board_init_f(ulong dummy)120 void board_init_f(ulong dummy)
121 {
122 int ret;
123
124 arch_cpu_init();
125
126 init_uart_clk(1);
127
128 ret = spl_early_init();
129 if (ret) {
130 debug("spl_init() failed: %d\n", ret);
131 hang();
132 }
133
134 preloader_console_init();
135
136 enable_tzc380();
137
138 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
139
140 power_init_board();
141
142 /* DDR initialization */
143 spl_dram_init();
144 }
145