1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <fdt_support.h>
10 #include <hang.h>
11 #include <i2c.h>
12 #include <asm/cache.h>
13 #include <init.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/fsl_serdes.h>
18 #ifdef CONFIG_FSL_LS_PPA
19 #include <asm/arch/ppa.h>
20 #endif
21 #include <asm/arch/mmu.h>
22 #include <asm/arch/soc.h>
23 #include <hwconfig.h>
24 #include <ahci.h>
25 #include <mmc.h>
26 #include <scsi.h>
27 #include <fsl_esdhc.h>
28 #include <env_internal.h>
29 #include <fsl_mmdc.h>
30 #include <netdev.h>
31 #include <net/pfe_eth/pfe/pfe_hw.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define BOOT_FROM_UPPER_BANK 0x2
36 #define BOOT_FROM_LOWER_BANK 0x1
37
checkboard(void)38 int checkboard(void)
39 {
40 #ifdef CONFIG_TARGET_LS1012ARDB
41 u8 in1;
42 int ret, bus_num = 0;
43
44 puts("Board: LS1012ARDB ");
45
46 /* Initialize i2c early for Serial flash bank information */
47 #if CONFIG_IS_ENABLED(DM_I2C)
48 struct udevice *dev;
49
50 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
51 1, &dev);
52 if (ret) {
53 printf("%s: Cannot find udev for a bus %d\n", __func__,
54 bus_num);
55 return -ENXIO;
56 }
57 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
58 #else /* Non DM I2C support - will be removed */
59 i2c_set_bus_num(bus_num);
60 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
61 #endif
62 if (ret < 0) {
63 printf("Error reading i2c boot information!\n");
64 return 0; /* Don't want to hang() on this error */
65 }
66
67 puts("Version");
68 switch (in1 & SW_REV_MASK) {
69 case SW_REV_A:
70 puts(": RevA");
71 break;
72 case SW_REV_B:
73 puts(": RevB");
74 break;
75 case SW_REV_C:
76 puts(": RevC");
77 break;
78 case SW_REV_C1:
79 puts(": RevC1");
80 break;
81 case SW_REV_C2:
82 puts(": RevC2");
83 break;
84 case SW_REV_D:
85 puts(": RevD");
86 break;
87 case SW_REV_E:
88 puts(": RevE");
89 break;
90 default:
91 puts(": unknown");
92 break;
93 }
94
95 printf(", boot from QSPI");
96 if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
97 puts(": emu\n");
98 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
99 puts(": bank1\n");
100 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
101 puts(": bank2\n");
102 else
103 puts("unknown\n");
104 #else
105
106 puts("Board: LS1012A2G5RDB ");
107 #endif
108 return 0;
109 }
110
111 #ifdef CONFIG_TFABOOT
dram_init(void)112 int dram_init(void)
113 {
114 gd->ram_size = tfa_get_dram_size();
115 if (!gd->ram_size)
116 gd->ram_size = CFG_SYS_SDRAM_SIZE;
117
118 return 0;
119 }
120 #else
dram_init(void)121 int dram_init(void)
122 {
123 #ifndef CONFIG_TFABOOT
124 static const struct fsl_mmdc_info mparam = {
125 0x05180000, /* mdctl */
126 0x00030035, /* mdpdc */
127 0x12554000, /* mdotc */
128 0xbabf7954, /* mdcfg0 */
129 0xdb328f64, /* mdcfg1 */
130 0x01ff00db, /* mdcfg2 */
131 0x00001680, /* mdmisc */
132 0x0f3c8000, /* mdref */
133 0x00002000, /* mdrwd */
134 0x00bf1023, /* mdor */
135 0x0000003f, /* mdasp */
136 0x0000022a, /* mpodtctrl */
137 0xa1390003, /* mpzqhwctrl */
138 };
139
140 mmdc_init(&mparam);
141 #endif
142
143 gd->ram_size = CFG_SYS_SDRAM_SIZE;
144 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
145 /* This will break-before-make MMU for DDR */
146 update_early_mmu_table();
147 #endif
148
149 return 0;
150 }
151 #endif
152
153
board_early_init_f(void)154 int board_early_init_f(void)
155 {
156 fsl_lsch2_early_init_f();
157
158 return 0;
159 }
160
board_init(void)161 int board_init(void)
162 {
163 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
164 CONFIG_SYS_CCI400_OFFSET);
165 /*
166 * Set CCI-400 control override register to enable barrier
167 * transaction
168 */
169 if (current_el() == 3)
170 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
171
172 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
173 erratum_a010315();
174 #endif
175
176 #ifdef CONFIG_FSL_LS_PPA
177 ppa_init();
178 #endif
179 return 0;
180 }
181
182 #ifdef CONFIG_FSL_PFE
board_quiesce_devices(void)183 void board_quiesce_devices(void)
184 {
185 pfe_command_stop(0, NULL);
186 }
187 #endif
188
189 #ifdef CONFIG_TARGET_LS1012ARDB
esdhc_status_fixup(void * blob,const char * compat)190 int esdhc_status_fixup(void *blob, const char *compat)
191 {
192 char esdhc1_path[] = "/soc/esdhc@1580000";
193 bool sdhc2_en = false;
194 u8 mux_sdhc2;
195 u8 io = 0;
196 int ret, bus_num = 0;
197
198 #if CONFIG_IS_ENABLED(DM_I2C)
199 struct udevice *dev;
200
201 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
202 1, &dev);
203 if (ret) {
204 printf("%s: Cannot find udev for a bus %d\n", __func__,
205 bus_num);
206 return -ENXIO;
207 }
208 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
209 #else
210 i2c_set_bus_num(bus_num);
211 /* IO1[7:3] is the field of board revision info. */
212 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
213 #endif
214 if (ret < 0) {
215 printf("Error reading i2c boot information!\n");
216 return 0;
217 }
218
219 /* hwconfig method is used for RevD and later versions. */
220 if ((io & SW_REV_MASK) <= SW_REV_D) {
221 #ifdef CONFIG_HWCONFIG
222 if (hwconfig("esdhc1"))
223 sdhc2_en = true;
224 #endif
225 } else {
226 /*
227 * The I2C IO-expander for mux select is used to control
228 * the muxing of various onboard interfaces.
229 *
230 * IO0[3:2] indicates SDHC2 interface demultiplexer
231 * select lines.
232 * 00 - SDIO wifi
233 * 01 - GPIO (to Arduino)
234 * 10 - eMMC Memory
235 * 11 - SPI
236 */
237 #if CONFIG_IS_ENABLED(DM_I2C)
238 ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
239 #else
240 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
241 #endif
242 if (ret < 0) {
243 printf("Error reading i2c boot information!\n");
244 return 0;
245 }
246
247 mux_sdhc2 = (io & 0x0c) >> 2;
248 /* Enable SDHC2 only when use SDIO wifi and eMMC */
249 if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
250 sdhc2_en = true;
251 }
252 if (sdhc2_en)
253 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
254 sizeof("okay"), 1);
255 else
256 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
257 sizeof("disabled"), 1);
258 return 0;
259 }
260 #endif
261
ft_board_setup(void * blob,struct bd_info * bd)262 int ft_board_setup(void *blob, struct bd_info *bd)
263 {
264 arch_fixup_fdt(blob);
265
266 ft_cpu_setup(blob, bd);
267
268 return 0;
269 }
270
switch_to_bank1(void)271 static int switch_to_bank1(void)
272 {
273 u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
274 int ret, bus_num = 0;
275
276 #if CONFIG_IS_ENABLED(DM_I2C)
277 struct udevice *dev;
278
279 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
280 1, &dev);
281 if (ret) {
282 printf("%s: Cannot find udev for a bus %d\n", __func__,
283 bus_num);
284 return -ENXIO;
285 }
286 /*
287 * --------------------------------------------------------------------
288 * |bus |I2C address| Device | Notes |
289 * --------------------------------------------------------------------
290 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
291 * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
292 * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
293 * | | | PCAL9555AHF | I2C bus |
294 * ----- --------------------------------------------------------------
295 * - mount three IO expander(PCAL9555AHF) on I2C1
296 *
297 * PCAL9555A device address
298 * slave address
299 * --------------------------------------
300 * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
301 * --------------------------------------
302 * | fixed | hardware selectable|
303 *
304 * Output port 1(Pinter register bits = 0x03)
305 *
306 * P1_[7~0] = 0xf4
307 * P1_0 <---> CFG_MUX_QSPI_S0
308 * P1_1 <---> CFG_MUX_QSPI_S1
309 * CFG_MUX_QSPI_S[1:0] = 0b00
310 *
311 * QSPI chip-select demultiplexer select
312 * ---------------------------------------------------------------------
313 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
314 * ---------------------------------------------------------------------
315 * 0 | 0 |CS routed to SPI memory bank1(default)
316 * ---------------------------------------------------------------------
317 * 0 | 1 |CS routed to SPI memory bank2
318 * ---------------------------------------------------------------------
319 *
320 */
321 ret = dm_i2c_write(dev, offset_addr, &data, 1);
322 #else /* Non DM I2C support - will be removed */
323 i2c_set_bus_num(bus_num);
324 ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
325 #endif
326
327 if (ret) {
328 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
329 chip_addr, offset_addr, data);
330 }
331
332 return ret;
333 }
334
switch_to_bank2(void)335 static int switch_to_bank2(void)
336 {
337 u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
338 u8 chip_addr = 0x24;
339 int ret, i, bus_num = 0;
340
341 #if CONFIG_IS_ENABLED(DM_I2C)
342 struct udevice *dev;
343
344 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
345 1, &dev);
346 if (ret) {
347 printf("%s: Cannot find udev for a bus %d\n", __func__,
348 bus_num);
349 return -ENXIO;
350 }
351 #else /* Non DM I2C support - will be removed */
352 i2c_set_bus_num(bus_num);
353 #endif
354
355 /*
356 * 1th step: config port 1
357 * - the port 1 pin is enabled as an output
358 * 2th step: output port 1
359 * - P1_[7:0] output 0xf5,
360 * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
361 * CS routed to SPI memory bank2
362 */
363 for (i = 0; i < sizeof(data); i++) {
364 #if CONFIG_IS_ENABLED(DM_I2C)
365 ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
366 #else /* Non DM I2C support - will be removed */
367 ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
368 #endif
369 if (ret) {
370 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
371 chip_addr, offset_addr[i], data[i]);
372 goto err;
373 }
374 }
375
376 err:
377 return ret;
378 }
379
convert_flash_bank(int bank)380 static int convert_flash_bank(int bank)
381 {
382 int ret = 0;
383
384 switch (bank) {
385 case BOOT_FROM_UPPER_BANK:
386 ret = switch_to_bank2();
387 break;
388 case BOOT_FROM_LOWER_BANK:
389 ret = switch_to_bank1();
390 break;
391 default:
392 ret = CMD_RET_USAGE;
393 break;
394 };
395
396 return ret;
397 }
398
flash_bank_cmd(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])399 static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
400 char *const argv[])
401 {
402 if (argc != 2)
403 return CMD_RET_USAGE;
404 if (strcmp(argv[1], "1") == 0)
405 convert_flash_bank(BOOT_FROM_LOWER_BANK);
406 else if (strcmp(argv[1], "2") == 0)
407 convert_flash_bank(BOOT_FROM_UPPER_BANK);
408 else
409 return CMD_RET_USAGE;
410
411 return 0;
412 }
413
414 U_BOOT_CMD(
415 boot_bank, 2, 0, flash_bank_cmd,
416 "Flash bank Selection Control",
417 "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
418 );
419