1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2019, 2021 NXP
5 */
6
7 #include <common.h>
8 #include <clock_legacy.h>
9 #include <fdt_support.h>
10 #include <i2c.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/io.h>
14 #include <asm/arch/immap_ls102xa.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/ls102xa_soc.h>
18 #include <asm/arch/ls102xa_devdis.h>
19 #include <hwconfig.h>
20 #include <mmc.h>
21 #include <fsl_csu.h>
22 #include <fsl_ifc.h>
23 #include <spl.h>
24 #include <fsl_devdis.h>
25 #include <fsl_validate.h>
26 #include <fsl_ddr.h>
27 #include "../common/i2c_mux.h"
28 #include "../common/sleep.h"
29 #include "../common/qixis.h"
30 #include "ls1021aqds_qixis.h"
31 #ifdef CONFIG_U_QE
32 #include <fsl_qe.h>
33 #endif
34
35 #define PIN_MUX_SEL_CAN 0x03
36 #define PIN_MUX_SEL_IIC2 0xa0
37 #define PIN_MUX_SEL_RGMII 0x00
38 #define PIN_MUX_SEL_SAI 0x0c
39 #define PIN_MUX_SEL_SDHC 0x00
40
41 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
42 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
43 enum {
44 MUX_TYPE_CAN,
45 MUX_TYPE_IIC2,
46 MUX_TYPE_RGMII,
47 MUX_TYPE_SAI,
48 MUX_TYPE_SDHC,
49 MUX_TYPE_SD_PCI4,
50 MUX_TYPE_SD_PC_SA_SG_SG,
51 MUX_TYPE_SD_PC_SA_PC_SG,
52 MUX_TYPE_SD_PC_SG_SG,
53 };
54
55 enum {
56 GE0_CLK125,
57 GE2_CLK125,
58 GE1_CLK125,
59 };
60
checkboard(void)61 int checkboard(void)
62 {
63 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
64 char buf[64];
65 #endif
66 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
67 u8 sw;
68 #endif
69
70 puts("Board: LS1021AQDS\n");
71
72 #ifdef CONFIG_SD_BOOT
73 puts("SD\n");
74 #elif CONFIG_QSPI_BOOT
75 puts("QSPI\n");
76 #else
77 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
79
80 if (sw < 0x8)
81 printf("vBank: %d\n", sw);
82 else if (sw == 0x8)
83 puts("PromJet\n");
84 else if (sw == 0x9)
85 puts("NAND\n");
86 else if (sw == 0x15)
87 printf("IFCCard\n");
88 else
89 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
90 #endif
91
92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
93 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
94 QIXIS_READ(id), QIXIS_READ(arch));
95
96 printf("FPGA: v%d (%s), build %d\n",
97 (int)QIXIS_READ(scver), qixis_read_tag(buf),
98 (int)qixis_read_minor());
99 #endif
100
101 return 0;
102 }
103
104 #ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
get_board_sys_clk(void)105 unsigned long get_board_sys_clk(void)
106 {
107 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
108
109 switch (sysclk_conf & 0x0f) {
110 case QIXIS_SYSCLK_64:
111 return 64000000;
112 case QIXIS_SYSCLK_83:
113 return 83333333;
114 case QIXIS_SYSCLK_100:
115 return 100000000;
116 case QIXIS_SYSCLK_125:
117 return 125000000;
118 case QIXIS_SYSCLK_133:
119 return 133333333;
120 case QIXIS_SYSCLK_150:
121 return 150000000;
122 case QIXIS_SYSCLK_160:
123 return 160000000;
124 case QIXIS_SYSCLK_166:
125 return 166666666;
126 }
127 return 66666666;
128 }
129 #endif
130
131 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
get_board_ddr_clk(void)132 unsigned long get_board_ddr_clk(void)
133 {
134 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
135
136 switch ((ddrclk_conf & 0x30) >> 4) {
137 case QIXIS_DDRCLK_100:
138 return 100000000;
139 case QIXIS_DDRCLK_125:
140 return 125000000;
141 case QIXIS_DDRCLK_133:
142 return 133333333;
143 }
144 return 66666666;
145 }
146 #endif
147
dram_init(void)148 int dram_init(void)
149 {
150 /*
151 * When resuming from deep sleep, the I2C channel may not be
152 * in the default channel. So, switch to the default channel
153 * before accessing DDR SPD.
154 *
155 * PCA9547(0x77) mount on I2C1 bus
156 */
157 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
158 return fsl_initdram();
159 }
160
board_early_init_f(void)161 int board_early_init_f(void)
162 {
163 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
164
165 #ifdef CONFIG_TSEC_ENET
166 /* clear BD & FR bits for BE BD's and frame data */
167 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
168 #endif
169
170 #ifdef CONFIG_FSL_IFC
171 init_early_memctl_regs();
172 #endif
173
174 arch_soc_init();
175
176 #if defined(CONFIG_DEEP_SLEEP)
177 if (is_warm_boot())
178 fsl_dp_disable_console();
179 #endif
180
181 return 0;
182 }
183
184 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)185 void board_init_f(ulong dummy)
186 {
187 #ifdef CONFIG_NAND_BOOT
188 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
189 u32 porsr1, pinctl;
190
191 /*
192 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
193 * NAND boot because IFC signals > IFC_AD7 are not enabled.
194 * This workaround changes RCW source to make all signals enabled.
195 */
196 porsr1 = in_be32(&gur->porsr1);
197 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
198 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
199 out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
200 pinctl);
201 #endif
202
203 /* Clear the BSS */
204 memset(__bss_start, 0, __bss_end - __bss_start);
205
206 #ifdef CONFIG_FSL_IFC
207 init_early_memctl_regs();
208 #endif
209
210 get_clocks();
211
212 #if defined(CONFIG_DEEP_SLEEP)
213 if (is_warm_boot())
214 fsl_dp_disable_console();
215 #endif
216
217 preloader_console_init();
218
219 #ifdef CONFIG_SPL_I2C
220 i2c_init_all();
221 #endif
222
223 timer_init();
224 dram_init();
225
226 /* Allow OCRAM access permission as R/W */
227 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
228 enable_layerscape_ns_access();
229 #endif
230
231 board_init_r(NULL, 0);
232 }
233 #endif
234
config_etseccm_source(int etsec_gtx_125_mux)235 void config_etseccm_source(int etsec_gtx_125_mux)
236 {
237 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
238
239 switch (etsec_gtx_125_mux) {
240 case GE0_CLK125:
241 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
242 debug("etseccm set to GE0_CLK125\n");
243 break;
244
245 case GE2_CLK125:
246 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
247 debug("etseccm set to GE2_CLK125\n");
248 break;
249
250 case GE1_CLK125:
251 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
252 debug("etseccm set to GE1_CLK125\n");
253 break;
254
255 default:
256 printf("Error! trying to set etseccm to invalid value\n");
257 break;
258 }
259 }
260
config_board_mux(int ctrl_type)261 int config_board_mux(int ctrl_type)
262 {
263 u8 reg12, reg14;
264
265 reg12 = QIXIS_READ(brdcfg[12]);
266 reg14 = QIXIS_READ(brdcfg[14]);
267
268 switch (ctrl_type) {
269 case MUX_TYPE_CAN:
270 config_etseccm_source(GE2_CLK125);
271 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
272 break;
273 case MUX_TYPE_IIC2:
274 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
275 break;
276 case MUX_TYPE_RGMII:
277 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
278 break;
279 case MUX_TYPE_SAI:
280 config_etseccm_source(GE2_CLK125);
281 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
282 break;
283 case MUX_TYPE_SDHC:
284 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
285 break;
286 case MUX_TYPE_SD_PCI4:
287 reg12 = 0x38;
288 break;
289 case MUX_TYPE_SD_PC_SA_SG_SG:
290 reg12 = 0x01;
291 break;
292 case MUX_TYPE_SD_PC_SA_PC_SG:
293 reg12 = 0x01;
294 break;
295 case MUX_TYPE_SD_PC_SG_SG:
296 reg12 = 0x21;
297 break;
298 default:
299 printf("Wrong mux interface type\n");
300 return -1;
301 }
302
303 QIXIS_WRITE(brdcfg[12], reg12);
304 QIXIS_WRITE(brdcfg[14], reg14);
305
306 return 0;
307 }
308
config_serdes_mux(void)309 int config_serdes_mux(void)
310 {
311 struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
312 u32 cfg;
313
314 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
315 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
316
317 switch (cfg) {
318 case 0x0:
319 config_board_mux(MUX_TYPE_SD_PCI4);
320 break;
321 case 0x30:
322 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
323 break;
324 case 0x60:
325 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
326 break;
327 case 0x70:
328 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
329 break;
330 default:
331 printf("SRDS1 prtcl:0x%x\n", cfg);
332 break;
333 }
334
335 return 0;
336 }
337
338 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)339 int board_late_init(void)
340 {
341 #ifdef CONFIG_CHAIN_OF_TRUST
342 fsl_setenv_chain_of_trust();
343 #endif
344
345 return 0;
346 }
347 #endif
348
misc_init_r(void)349 int misc_init_r(void)
350 {
351 int conflict_flag;
352
353 /* some signals can not enable simultaneous*/
354 conflict_flag = 0;
355 if (hwconfig("sdhc"))
356 conflict_flag++;
357 if (hwconfig("iic2"))
358 conflict_flag++;
359 if (conflict_flag > 1) {
360 printf("WARNING: pin conflict !\n");
361 return 0;
362 }
363
364 conflict_flag = 0;
365 if (hwconfig("rgmii"))
366 conflict_flag++;
367 if (hwconfig("can"))
368 conflict_flag++;
369 if (hwconfig("sai"))
370 conflict_flag++;
371 if (conflict_flag > 1) {
372 printf("WARNING: pin conflict !\n");
373 return 0;
374 }
375
376 if (hwconfig("can"))
377 config_board_mux(MUX_TYPE_CAN);
378 else if (hwconfig("rgmii"))
379 config_board_mux(MUX_TYPE_RGMII);
380 else if (hwconfig("sai"))
381 config_board_mux(MUX_TYPE_SAI);
382
383 if (hwconfig("iic2"))
384 config_board_mux(MUX_TYPE_IIC2);
385 else if (hwconfig("sdhc"))
386 config_board_mux(MUX_TYPE_SDHC);
387
388 #ifdef CONFIG_FSL_DEVICE_DISABLE
389 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
390 #endif
391 return 0;
392 }
393
board_init(void)394 int board_init(void)
395 {
396 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
397 erratum_a010315();
398 #endif
399 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
400 erratum_a009942_check_cpo();
401 #endif
402
403 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
404
405 #ifndef CONFIG_SYS_FSL_NO_SERDES
406 fsl_serdes_init();
407 config_serdes_mux();
408 #endif
409
410 ls102xa_smmu_stream_id_init();
411
412 #ifdef CONFIG_U_QE
413 u_qe_init();
414 #endif
415
416 return 0;
417 }
418
419 #if defined(CONFIG_DEEP_SLEEP)
board_sleep_prepare(void)420 void board_sleep_prepare(void)
421 {
422 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
423 enable_layerscape_ns_access();
424 #endif
425 }
426 #endif
427
ft_board_setup(void * blob,struct bd_info * bd)428 int ft_board_setup(void *blob, struct bd_info *bd)
429 {
430 ft_cpu_setup(blob, bd);
431
432 #ifdef CONFIG_PCI
433 ft_pci_setup(blob, bd);
434 #endif
435
436 return 0;
437 }
438
flash_read8(void * addr)439 u8 flash_read8(void *addr)
440 {
441 return __raw_readb(addr + 1);
442 }
443
flash_write16(u16 val,void * addr)444 void flash_write16(u16 val, void *addr)
445 {
446 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
447
448 __raw_writew(shftval, addr);
449 }
450
flash_read16(void * addr)451 u16 flash_read16(void *addr)
452 {
453 u16 val = __raw_readw(addr);
454
455 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
456 }
457