1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor
4 * Copyright 2021 NXP
5 */
6 #include <common.h>
7 #include <clock_legacy.h>
8 #include <display_options.h>
9 #include <env.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <errno.h>
13 #include <netdev.h>
14 #include <fsl_ifc.h>
15 #include <fsl_ddr.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <fdt_support.h>
19 #include <linux/libfdt.h>
20 #include <fsl-mc/fsl_mc.h>
21 #include <env_internal.h>
22 #include <i2c.h>
23 #include <rtc.h>
24 #include <asm/arch/soc.h>
25 #include <hwconfig.h>
26 #include <asm/arch/ppa.h>
27 #include <asm/arch-fsl-layerscape/fsl_icid.h>
28 #include "../common/i2c_mux.h"
29
30 #include "../common/qixis.h"
31 #include "ls2080aqds_qixis.h"
32 #include "../common/vid.h"
33
34 #define PIN_MUX_SEL_SDHC 0x00
35 #define PIN_MUX_SEL_DSPI 0x0a
36 #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
37
38 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 enum {
43 MUX_TYPE_SDHC,
44 MUX_TYPE_DSPI,
45 };
46
get_qixis_addr(void)47 unsigned long long get_qixis_addr(void)
48 {
49 unsigned long long addr;
50
51 if (gd->flags & GD_FLG_RELOC)
52 addr = QIXIS_BASE_PHYS;
53 else
54 addr = QIXIS_BASE_PHYS_EARLY;
55
56 /*
57 * IFC address under 256MB is mapped to 0x30000000, any address above
58 * is mapped to 0x5_10000000 up to 4GB.
59 */
60 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
61
62 return addr;
63 }
64
checkboard(void)65 int checkboard(void)
66 {
67 char buf[64];
68 u8 sw;
69 static const char *const freq[] = {"100", "125", "156.25",
70 "100 separate SSCG"};
71 int clock;
72
73 cpu_name(buf);
74 printf("Board: %s-QDS, ", buf);
75
76 sw = QIXIS_READ(arch);
77 printf("Board Arch: V%d, ", sw >> 4);
78 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
79
80 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
81
82 sw = QIXIS_READ(brdcfg[0]);
83 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
84
85 if (sw < 0x8)
86 printf("vBank: %d\n", sw);
87 else if (sw == 0x8)
88 puts("PromJet\n");
89 else if (sw == 0x9)
90 puts("NAND\n");
91 else if (sw == 0xf)
92 puts("QSPI\n");
93 else if (sw == 0x15)
94 printf("IFCCard\n");
95 else
96 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
97
98 printf("FPGA: v%d (%s), build %d",
99 (int)QIXIS_READ(scver), qixis_read_tag(buf),
100 (int)qixis_read_minor());
101 /* the timestamp string contains "\n" at the end */
102 printf(" on %s", qixis_read_time(buf));
103
104 /*
105 * Display the actual SERDES reference clocks as configured by the
106 * dip switches on the board. Note that the SWx registers could
107 * technically be set to force the reference clocks to match the
108 * values that the SERDES expects (or vice versa). For now, however,
109 * we just display both values and hope the user notices when they
110 * don't match.
111 */
112 puts("SERDES1 Reference : ");
113 sw = QIXIS_READ(brdcfg[2]);
114 clock = (sw >> 6) & 3;
115 printf("Clock1 = %sMHz ", freq[clock]);
116 clock = (sw >> 4) & 3;
117 printf("Clock2 = %sMHz", freq[clock]);
118
119 puts("\nSERDES2 Reference : ");
120 clock = (sw >> 2) & 3;
121 printf("Clock1 = %sMHz ", freq[clock]);
122 clock = (sw >> 0) & 3;
123 printf("Clock2 = %sMHz\n", freq[clock]);
124
125 return 0;
126 }
127
get_board_sys_clk(void)128 unsigned long get_board_sys_clk(void)
129 {
130 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
131
132 switch (sysclk_conf & 0x0F) {
133 case QIXIS_SYSCLK_83:
134 return 83333333;
135 case QIXIS_SYSCLK_100:
136 return 100000000;
137 case QIXIS_SYSCLK_125:
138 return 125000000;
139 case QIXIS_SYSCLK_133:
140 return 133333333;
141 case QIXIS_SYSCLK_150:
142 return 150000000;
143 case QIXIS_SYSCLK_160:
144 return 160000000;
145 case QIXIS_SYSCLK_166:
146 return 166666666;
147 }
148 return 66666666;
149 }
150
get_board_ddr_clk(void)151 unsigned long get_board_ddr_clk(void)
152 {
153 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
154
155 switch ((ddrclk_conf & 0x30) >> 4) {
156 case QIXIS_DDRCLK_100:
157 return 100000000;
158 case QIXIS_DDRCLK_125:
159 return 125000000;
160 case QIXIS_DDRCLK_133:
161 return 133333333;
162 }
163 return 66666666;
164 }
165
config_board_mux(int ctrl_type)166 int config_board_mux(int ctrl_type)
167 {
168 u8 reg5;
169
170 reg5 = QIXIS_READ(brdcfg[5]);
171
172 switch (ctrl_type) {
173 case MUX_TYPE_SDHC:
174 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
175 break;
176 case MUX_TYPE_DSPI:
177 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
178 break;
179 default:
180 printf("Wrong mux interface type\n");
181 return -1;
182 }
183
184 QIXIS_WRITE(brdcfg[5], reg5);
185
186 return 0;
187 }
188
board_init(void)189 int board_init(void)
190 {
191 char *env_hwconfig;
192 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
193 u32 val;
194
195 init_final_memctl_regs();
196
197 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
198
199 env_hwconfig = env_get("hwconfig");
200
201 if (hwconfig_f("dspi", env_hwconfig) &&
202 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
203 config_board_mux(MUX_TYPE_DSPI);
204 else
205 config_board_mux(MUX_TYPE_SDHC);
206
207 #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
208 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
209
210 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
211 QIXIS_WRITE(brdcfg[9],
212 (QIXIS_READ(brdcfg[9]) & 0xf8) |
213 FSL_QIXIS_BRDCFG9_QSPI);
214 #endif
215
216 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
217
218 #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
219 #if CONFIG_IS_ENABLED(DM_I2C)
220 rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
221 #else
222 rtc_enable_32khz_output();
223 #endif
224 #endif
225
226 #ifdef CONFIG_FSL_LS_PPA
227 ppa_init();
228 #endif
229
230 #if !defined(CONFIG_SYS_EARLY_PCI_INIT)
231 pci_init();
232 #endif
233
234 return 0;
235 }
236
board_early_init_f(void)237 int board_early_init_f(void)
238 {
239 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
240 i2c_early_init_f();
241 #endif
242 fsl_lsch3_early_init_f();
243 #ifdef CONFIG_FSL_QSPI
244 /* input clk: 1/2 platform clk, output: input/20 */
245 out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
246 #endif
247 return 0;
248 }
249
misc_init_r(void)250 int misc_init_r(void)
251 {
252 if (adjust_vdd(0))
253 printf("Warning: Adjusting core voltage failed.\n");
254
255 return 0;
256 }
257
detail_board_ddr_info(void)258 void detail_board_ddr_info(void)
259 {
260 puts("\nDDR ");
261 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
262 print_ddr_info(0);
263 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
264 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
265 puts("\nDP-DDR ");
266 print_size(gd->bd->bi_dram[2].size, "");
267 print_ddr_info(CONFIG_DP_DDR_CTRL);
268 }
269 #endif
270 }
271
272 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(void * fdt)273 void fdt_fixup_board_enet(void *fdt)
274 {
275 int offset;
276
277 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
278
279 if (offset < 0)
280 offset = fdt_path_offset(fdt, "/fsl-mc");
281
282 if (offset < 0) {
283 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
284 __func__, offset);
285 return;
286 }
287
288 if (get_mc_boot_status() == 0 &&
289 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
290 fdt_status_okay(fdt, offset);
291 else
292 fdt_status_fail(fdt, offset);
293 }
294
board_quiesce_devices(void)295 void board_quiesce_devices(void)
296 {
297 fsl_mc_ldpaa_exit(gd->bd);
298 }
299 #endif
300
301 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)302 int ft_board_setup(void *blob, struct bd_info *bd)
303 {
304 u64 base[CONFIG_NR_DRAM_BANKS];
305 u64 size[CONFIG_NR_DRAM_BANKS];
306
307 ft_cpu_setup(blob, bd);
308
309 /* fixup DT for the two GPP DDR banks */
310 base[0] = gd->bd->bi_dram[0].start;
311 size[0] = gd->bd->bi_dram[0].size;
312 base[1] = gd->bd->bi_dram[1].start;
313 size[1] = gd->bd->bi_dram[1].size;
314
315 #ifdef CONFIG_RESV_RAM
316 /* reduce size if reserved memory is within this bank */
317 if (gd->arch.resv_ram >= base[0] &&
318 gd->arch.resv_ram < base[0] + size[0])
319 size[0] = gd->arch.resv_ram - base[0];
320 else if (gd->arch.resv_ram >= base[1] &&
321 gd->arch.resv_ram < base[1] + size[1])
322 size[1] = gd->arch.resv_ram - base[1];
323 #endif
324
325 fdt_fixup_memory_banks(blob, base, size, 2);
326
327 fdt_fsl_mc_fixup_iommu_map_entry(blob);
328
329 fsl_fdt_fixup_dr_usb(blob, bd);
330
331 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
332 fdt_fixup_board_enet(blob);
333 #endif
334
335 fdt_fixup_icid(blob);
336
337 return 0;
338 }
339 #endif
340
qixis_dump_switch(void)341 void qixis_dump_switch(void)
342 {
343 int i, nr_of_cfgsw;
344
345 QIXIS_WRITE(cms[0], 0x00);
346 nr_of_cfgsw = QIXIS_READ(cms[1]);
347
348 puts("DIP switch settings dump:\n");
349 for (i = 1; i <= nr_of_cfgsw; i++) {
350 QIXIS_WRITE(cms[0], i);
351 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
352 }
353 }
354