1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <vsprintf.h>
8 #include <asm/global_data.h>
9 #include <asm/mmu.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/processor.h>
12 #include <fsl_ddr_sdram.h>
13 #include <fsl_ddr_dimm_params.h>
14 #include <asm/io.h>
15 #include <asm/fsl_law.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /*
20 * Samsung K4B2G0846C-HCF8
21 * The following timing are for "downshift"
22 * i.e. to use CL9 part as CL7
23 * otherwise, tAA, tRCD, tRP will be 13500ps
24 * and tRC will be 49500ps
25 */
26 dimm_params_t ddr_raw_timing = {
27 .n_ranks = 1,
28 .rank_density = 1073741824u,
29 .capacity = 1073741824u,
30 .primary_sdram_width = 32,
31 .ec_sdram_width = 0,
32 .registered_dimm = 0,
33 .mirrored_dimm = 0,
34 .n_row_addr = 15,
35 .n_col_addr = 10,
36 .n_banks_per_sdram_device = 8,
37 .edc_config = 0,
38 .burst_lengths_bitmask = 0x0c,
39
40 .tckmin_x_ps = 1875,
41 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
42 .taa_ps = 13125,
43 .twr_ps = 15000,
44 .trcd_ps = 13125,
45 .trrd_ps = 7500,
46 .trp_ps = 13125,
47 .tras_ps = 37500,
48 .trc_ps = 50625,
49 .trfc_ps = 160000,
50 .twtr_ps = 7500,
51 .trtp_ps = 7500,
52 .refresh_rate_ps = 7800000,
53 .tfaw_ps = 37500,
54 };
55
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)56 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
57 unsigned int controller_number,
58 unsigned int dimm_number)
59 {
60 const char dimm_model[] = "Fixed DDR on board";
61
62 if ((controller_number == 0) && (dimm_number == 0)) {
63 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
64 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
65 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
66 }
67
68 return 0;
69 }
70
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)71 void fsl_ddr_board_options(memctl_options_t *popts,
72 dimm_params_t *pdimm,
73 unsigned int ctrl_num)
74 {
75 struct cpu_type *cpu;
76 int i;
77 popts->clk_adjust = 6;
78 popts->cpo_override = 0x1f;
79 popts->write_data_delay = 2;
80 popts->half_strength_driver_enable = 1;
81 /* Write leveling override */
82 popts->wrlvl_en = 1;
83 popts->wrlvl_override = 1;
84 popts->wrlvl_sample = 0xf;
85 popts->wrlvl_start = 0x8;
86 popts->trwt_override = 1;
87 popts->trwt = 0;
88
89 cpu = gd->arch.cpu;
90 /* P1014 and it's derivatives support max 16it DDR width */
91 if (cpu->soc_ver == SVR_P1014)
92 popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
93
94 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
95 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
96 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
97 }
98 }
99