1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020 NXP
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <env.h>
10 #include <fdt_support.h>
11 #include <i2c.h>
12 #include <image.h>
13 #include <init.h>
14 #include <netdev.h>
15 #include <asm/global_data.h>
16 #include <linux/compiler.h>
17 #include <asm/mmu.h>
18 #include <asm/processor.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_liodn.h>
23 #include <fm_eth.h>
24 #include "t102xrdb.h"
25 #ifdef CONFIG_TARGET_T1024RDB
26 #include "cpld.h"
27 #elif defined(CONFIG_TARGET_T1023RDB)
28 #include <i2c.h>
29 #include <mmc.h>
30 #endif
31 #include "../common/sleep.h"
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #ifdef CONFIG_TARGET_T1023RDB
36 enum {
37 GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
38 GPIO1_EMMC_SEL,
39 GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
40 GPIO3_BRD_VER_MASK = 0x0c000000,
41 GPIO3_OFFSET = 0x2000,
42 I2C_GET_BANK,
43 I2C_SET_BANK0,
44 I2C_SET_BANK4,
45 };
46 #endif
47
checkboard(void)48 int checkboard(void)
49 {
50 struct cpu_type *cpu = gd->arch.cpu;
51 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
52 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
53 u32 srds_s1;
54
55 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
56 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
57
58 printf("Board: %sRDB, ", cpu->name);
59 #if defined(CONFIG_TARGET_T1024RDB)
60 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
61 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
62 #elif defined(CONFIG_TARGET_T1023RDB)
63 printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
64 #endif
65 printf("boot from ");
66
67 #ifdef CONFIG_SDCARD
68 puts("SD/MMC\n");
69 #elif CONFIG_SPIFLASH
70 puts("SPI\n");
71 #elif defined(CONFIG_TARGET_T1024RDB)
72 u8 reg;
73
74 reg = CPLD_READ(flash_csr);
75
76 if (reg & CPLD_BOOT_SEL) {
77 puts("NAND\n");
78 } else {
79 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
80 printf("NOR vBank%d\n", reg);
81 }
82 #elif defined(CONFIG_TARGET_T1023RDB)
83 #ifdef CONFIG_MTD_RAW_NAND
84 puts("NAND\n");
85 #else
86 printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
87 #endif
88 #endif
89
90 puts("SERDES Reference Clocks:\n");
91 if (srds_s1 == 0x95)
92 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
93 else
94 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
95
96 return 0;
97 }
98
99 #ifdef CONFIG_TARGET_T1024RDB
board_mux_lane(void)100 static void board_mux_lane(void)
101 {
102 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
103 u32 srds_prtcl_s1;
104 u8 reg = CPLD_READ(misc_ctl_status);
105
106 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
107 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
108 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
109
110 if (srds_prtcl_s1 == 0x95) {
111 /* Route Lane B to PCIE */
112 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
113 } else {
114 /* Route Lane B to SGMII */
115 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
116 }
117 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
118 }
119 #endif
120
board_early_init_f(void)121 int board_early_init_f(void)
122 {
123 #if defined(CONFIG_DEEP_SLEEP)
124 if (is_warm_boot())
125 fsl_dp_disable_console();
126 #endif
127
128 return 0;
129 }
130
board_early_init_r(void)131 int board_early_init_r(void)
132 {
133 #ifdef CFG_SYS_FLASH_BASE
134 const unsigned int flashbase = CFG_SYS_FLASH_BASE;
135 int flash_esel = find_tlb_idx((void *)flashbase, 1);
136 /*
137 * Remap Boot flash region to caching-inhibited
138 * so that flash can be erased properly.
139 */
140
141 /* Flush d-cache and invalidate i-cache of any FLASH data */
142 flush_dcache();
143 invalidate_icache();
144 if (flash_esel == -1) {
145 /* very unlikely unless something is messed up */
146 puts("Error: Could not find TLB for FLASH BASE\n");
147 flash_esel = 2; /* give our best effort to continue */
148 } else {
149 /* invalidate existing TLB entry for flash + promjet */
150 disable_tlb(flash_esel);
151 }
152
153 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
154 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
155 0, flash_esel, BOOKE_PAGESZ_256M, 1);
156 #endif
157
158 #ifdef CONFIG_TARGET_T1024RDB
159 board_mux_lane();
160 #endif
161
162 return 0;
163 }
164
165 #ifdef CONFIG_TARGET_T1024RDB
board_reset(void)166 void board_reset(void)
167 {
168 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
169 }
170 #endif
171
misc_init_r(void)172 int misc_init_r(void)
173 {
174 return 0;
175 }
176
ft_board_setup(void * blob,struct bd_info * bd)177 int ft_board_setup(void *blob, struct bd_info *bd)
178 {
179 phys_addr_t base;
180 phys_size_t size;
181
182 ft_cpu_setup(blob, bd);
183
184 base = env_get_bootm_low();
185 size = env_get_bootm_size();
186
187 fdt_fixup_memory(blob, (u64)base, (u64)size);
188
189 #ifdef CONFIG_PCI
190 pci_of_setup(blob, bd);
191 #endif
192
193 fdt_fixup_liodn(blob);
194 fsl_fdt_fixup_dr_usb(blob, bd);
195
196 #ifdef CONFIG_SYS_DPAA_FMAN
197 #ifndef CONFIG_DM_ETH
198 fdt_fixup_fman_ethernet(blob);
199 #endif
200 fdt_fixup_board_enet(blob);
201 #endif
202
203 #ifdef CONFIG_TARGET_T1023RDB
204 if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
205 fdt_enable_nor(blob);
206 #endif
207
208 return 0;
209 }
210
211 #ifdef CONFIG_TARGET_T1023RDB
212 /* Enable NOR flash for RevC */
fdt_enable_nor(void * blob)213 static void fdt_enable_nor(void *blob)
214 {
215 int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
216
217 if (nodeoff >= 0)
218 fdt_status_okay(blob, nodeoff);
219 else
220 printf("WARNING unable to set status for NOR\n");
221 }
222
board_mmc_getcd(struct mmc * mmc)223 int board_mmc_getcd(struct mmc *mmc)
224 {
225 ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
226 u32 val = in_be32(&pgpio->gpdat);
227
228 /* GPIO1_14, 0: eMMC, 1: SD/MMC */
229 val &= GPIO1_SD_SEL;
230
231 return val ? -1 : 1;
232 }
233
board_mmc_getwp(struct mmc * mmc)234 int board_mmc_getwp(struct mmc *mmc)
235 {
236 ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
237 u32 val = in_be32(&pgpio->gpdat);
238
239 val &= GPIO1_SD_SEL;
240
241 return val ? -1 : 0;
242 }
243
t1023rdb_ctrl(u32 ctrl_type)244 static u32 t1023rdb_ctrl(u32 ctrl_type)
245 {
246 ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
247 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
248 u32 val;
249 u8 tmp;
250 int bus_num = I2C_PCA6408_BUS_NUM;
251
252 #if CONFIG_IS_ENABLED(DM_I2C)
253 struct udevice *dev;
254 int ret;
255
256 ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
257 1, &dev);
258 if (ret) {
259 printf("%s: Cannot find udev for a bus %d\n", __func__,
260 bus_num);
261 return ret;
262 }
263 switch (ctrl_type) {
264 case GPIO1_SD_SEL:
265 val = in_be32(&pgpio->gpdat);
266 val |= GPIO1_SD_SEL;
267 out_be32(&pgpio->gpdat, val);
268 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
269 break;
270 case GPIO1_EMMC_SEL:
271 val = in_be32(&pgpio->gpdat);
272 val &= ~GPIO1_SD_SEL;
273 out_be32(&pgpio->gpdat, val);
274 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
275 break;
276 case GPIO3_GET_VERSION:
277 pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
278 + GPIO3_OFFSET);
279 val = in_be32(&pgpio->gpdat);
280 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
281 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
282 val = 0;
283 return val;
284 case I2C_GET_BANK:
285 dm_i2c_read(dev, 0, &tmp, 1);
286 tmp &= 0x7;
287 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
288 return tmp;
289 case I2C_SET_BANK0:
290 tmp = 0x0;
291 dm_i2c_write(dev, 1, &tmp, 1);
292 tmp = 0xf8;
293 dm_i2c_write(dev, 3, &tmp, 1);
294 /* asserting HRESET_REQ */
295 out_be32(&gur->rstcr, 0x2);
296 break;
297 case I2C_SET_BANK4:
298 tmp = 0x1;
299 dm_i2c_write(dev, 1, &tmp, 1);
300 tmp = 0xf8;
301 dm_i2c_write(dev, 3, &tmp, 1);
302 out_be32(&gur->rstcr, 0x2);
303 break;
304 default:
305 break;
306 }
307 #else
308 u32 orig_bus;
309
310 orig_bus = i2c_get_bus_num();
311
312 switch (ctrl_type) {
313 case GPIO1_SD_SEL:
314 val = in_be32(&pgpio->gpdat);
315 val |= GPIO1_SD_SEL;
316 out_be32(&pgpio->gpdat, val);
317 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
318 break;
319 case GPIO1_EMMC_SEL:
320 val = in_be32(&pgpio->gpdat);
321 val &= ~GPIO1_SD_SEL;
322 out_be32(&pgpio->gpdat, val);
323 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
324 break;
325 case GPIO3_GET_VERSION:
326 pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
327 + GPIO3_OFFSET);
328 val = in_be32(&pgpio->gpdat);
329 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
330 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
331 val = 0;
332 return val;
333 case I2C_GET_BANK:
334 i2c_set_bus_num(bus_num);
335 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
336 tmp &= 0x7;
337 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
338 i2c_set_bus_num(orig_bus);
339 return tmp;
340 case I2C_SET_BANK0:
341 i2c_set_bus_num(bus_num);
342 tmp = 0x0;
343 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
344 tmp = 0xf8;
345 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
346 /* asserting HRESET_REQ */
347 out_be32(&gur->rstcr, 0x2);
348 break;
349 case I2C_SET_BANK4:
350 i2c_set_bus_num(bus_num);
351 tmp = 0x1;
352 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
353 tmp = 0xf8;
354 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
355 out_be32(&gur->rstcr, 0x2);
356 break;
357 default:
358 break;
359 }
360 #endif
361 return 0;
362 }
363
switch_cmd(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])364 static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
365 char *const argv[])
366 {
367 if (argc < 2)
368 return CMD_RET_USAGE;
369 if (!strcmp(argv[1], "bank0"))
370 t1023rdb_ctrl(I2C_SET_BANK0);
371 else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
372 t1023rdb_ctrl(I2C_SET_BANK4);
373 else if (!strcmp(argv[1], "sd"))
374 t1023rdb_ctrl(GPIO1_SD_SEL);
375 else if (!strcmp(argv[1], "emmc"))
376 t1023rdb_ctrl(GPIO1_EMMC_SEL);
377 else
378 return CMD_RET_USAGE;
379 return 0;
380 }
381
382 U_BOOT_CMD(
383 switch, 2, 0, switch_cmd,
384 "for bank0/bank4/sd/emmc switch control in runtime",
385 "command (e.g. switch bank4)"
386 );
387 #endif
388