1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <hang.h>
10 #include <image.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <errno.h>
16 #include <asm/io.h>
17 #include <asm/arch/ddr.h>
18 #include <asm/arch/imx8mq_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/clock.h>
21 #include <asm/mach-imx/iomux-v3.h>
22 #include <asm/mach-imx/gpio.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <fsl_esdhc_imx.h>
25 #include <mmc.h>
26 #include <linux/delay.h>
27 #include <power/pmic.h>
28 #include <spl.h>
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 extern struct dram_timing_info dram_timing_ch2;
33
spl_dram_init(void)34 static void spl_dram_init(void)
35 {
36 ddr_init(&dram_timing_ch2);
37 }
38
39 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
40 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
41 static struct i2c_pads_info i2c_pad_info1 = {
42 .scl = {
43 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
44 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
45 .gp = IMX_GPIO_NR(5, 14),
46 },
47 .sda = {
48 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
49 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
50 .gp = IMX_GPIO_NR(5, 15),
51 },
52 };
53
54 #define USDHC2_VSEL IMX_GPIO_NR(1, 8)
55 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
56 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
57
board_mmc_getcd(struct mmc * mmc)58 int board_mmc_getcd(struct mmc *mmc)
59 {
60 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
61 int ret = 0;
62
63 switch (cfg->esdhc_base) {
64 case USDHC1_BASE_ADDR:
65 ret = 1;
66 break;
67 case USDHC2_BASE_ADDR:
68 ret = !gpio_get_value(USDHC2_CD_GPIO);
69 return ret;
70 }
71
72 return 1;
73 }
74
75 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
76 PAD_CTL_FSEL2)
77 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
78
79 static iomux_v3_cfg_t const usdhc1_pads[] = {
80 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
91 };
92
93 static iomux_v3_cfg_t const usdhc2_pads[] = {
94 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
95 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
96 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
97 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
98 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
99 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
100 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
101 IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
102 };
103
104 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
105 {USDHC1_BASE_ADDR, 0, 8},
106 {USDHC2_BASE_ADDR, 0, 4},
107 };
108
board_mmc_init(struct bd_info * bis)109 int board_mmc_init(struct bd_info *bis)
110 {
111 int i, ret;
112 /*
113 * According to the board_mmc_init() the following map is done:
114 * (U-Boot device node) (Physical Port)
115 * mmc0 USDHC1
116 * mmc1 USDHC2
117 */
118 for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
119 switch (i) {
120 case 0:
121 init_clk_usdhc(0);
122 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
123 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
124 ARRAY_SIZE(usdhc1_pads));
125 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
126 gpio_direction_output(USDHC1_PWR_GPIO, 0);
127 udelay(500);
128 gpio_direction_output(USDHC1_PWR_GPIO, 1);
129 break;
130 case 1:
131 init_clk_usdhc(1);
132 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
133 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
134 ARRAY_SIZE(usdhc2_pads));
135 gpio_request(USDHC2_VSEL, "usdhc2_vsel");
136 gpio_direction_output(USDHC2_VSEL, 0);
137 break;
138 default:
139 printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
140 return -EINVAL;
141 }
142
143 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
144 if (ret)
145 return ret;
146 }
147
148 return 0;
149 }
150
151 #define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
152 #define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
153 #define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
154 #define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
155
156 #define I2C_MUX_ADDR 0x70
157 #define I2C_FAN53555_ADDR 0x60
158
159 static iomux_v3_cfg_t const power_pads[] = {
160 IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
161 };
162
power_init_board(void)163 int power_init_board(void)
164 {
165 uint8_t val;
166
167 imx_iomux_v3_setup_multiple_pads(power_pads,
168 ARRAY_SIZE(usdhc2_pads));
169
170 /* Release I2C multiplexer reset */
171 gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
172 gpio_direction_output(I2C1_PCA9546_RESET, 1);
173
174 /* Select VSEL0 on voltage regulators */
175 gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
176 gpio_direction_output(ARM_DRAM_VSEL, 0);
177 gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
178 gpio_direction_output(DRAM_1P1_VSEL, 0);
179 gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
180 gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
181
182 /* Set mux to target ARM/DRAM regulator */
183 i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
184 /* .6 + .40 = 1.00 */
185 val = 0x80 + 40;
186 i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
187 i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
188
189 /* Set mux to target DRAM regulator */
190 i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
191 /* .6 + .50 = 1.10 */
192 val = 0x80 + 50;
193 i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
194 i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
195
196 /* Set mux to target SoC/GPU/VPU regulator */
197 i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
198 /* .6 + .30 = .90 */
199 val = 0x80 + 30;
200 i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
201 i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
202
203 /* Set mux to target peripherals */
204 i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
205
206 return 0;
207 }
208
spl_board_init(void)209 void spl_board_init(void)
210 {
211 puts("Normal Boot\n");
212 }
213
214 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)215 int board_fit_config_name_match(const char *name)
216 {
217 /* Just empty function now - can't decide what to choose */
218 debug("%s: %s\n", __func__, name);
219
220 return 0;
221 }
222 #endif
223
board_init_f(ulong dummy)224 void board_init_f(ulong dummy)
225 {
226 int ret;
227
228 /* Clear global data */
229 memset((void *)gd, 0, sizeof(gd_t));
230
231 arch_cpu_init();
232
233 init_uart_clk(0);
234
235 board_early_init_f();
236
237 timer_init();
238
239 preloader_console_init();
240
241 /* Clear the BSS. */
242 memset(__bss_start, 0, __bss_end - __bss_start);
243
244 ret = spl_init();
245 if (ret) {
246 debug("spl_init() failed: %d\n", ret);
247 hang();
248 }
249
250 enable_tzc380();
251
252 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
253
254 power_init_board();
255
256 /* DDR initialization */
257 spl_dram_init();
258
259 board_init_r(NULL, 0);
260 }
261