1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Based on vendor support provided by AVNET Embedded
4 *
5 * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
6 * Copyright 2021 General Electric Company
7 * Copyright 2021 Collabora Ltd.
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <fsl_esdhc_imx.h>
13 #include <hang.h>
14 #include <i2c.h>
15 #include <image.h>
16 #include <init.h>
17 #include <log.h>
18 #include <mmc.h>
19 #include <spl.h>
20 #include <asm/global_data.h>
21 #include <asm/io.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/ddr.h>
24 #include <asm/arch/imx8mp_pins.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/mach-imx/boot_mode.h>
27 #include <asm/mach-imx/gpio.h>
28 #include <asm/mach-imx/iomux-v3.h>
29 #include <asm/mach-imx/mxc_i2c.h>
30 #include <dm/uclass.h>
31 #include <dm/device.h>
32 #include <linux/delay.h>
33 #include <power/pmic.h>
34 #include <power/rn5t567_pmic.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
spl_board_boot_device(enum boot_device boot_dev_spl)38 int spl_board_boot_device(enum boot_device boot_dev_spl)
39 {
40 return BOOT_DEVICE_BOOTROM;
41 }
42
spl_dram_init(void)43 void spl_dram_init(void)
44 {
45 ddr_init(&dram_timing);
46 }
47
spl_board_init(void)48 void spl_board_init(void)
49 {
50 /*
51 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
52 * not allow to change it. Should set the clock after PMIC
53 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
54 * set by ROM for ND VDD_SOC
55 */
56 clock_enable(CCGR_GIC, 0);
57 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
58 clock_enable(CCGR_GIC, 1);
59
60 puts("Normal Boot\n");
61 }
62
63 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \
64 | PAD_CTL_PE | PAD_CTL_FSEL2)
65 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
66 #define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \
67 | PAD_CTL_DSE4)
68
69 static const iomux_v3_cfg_t usdhc2_pads[] = {
70 MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
77 MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
78 MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
79 };
80
81 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
82 #define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19)
83
84 static const iomux_v3_cfg_t usdhc3_pads[] = {
85 MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97
98 };
99
100 static struct fsl_esdhc_cfg usdhc_cfg[] = {
101 { USDHC2_BASE_ADDR, 0, 4 },
102 { USDHC3_BASE_ADDR, 0, 8 },
103 };
104
board_mmc_init(struct bd_info * bis)105 int board_mmc_init(struct bd_info *bis)
106 {
107 int i, ret;
108 /*
109 * According to the board_mmc_init() the following map is done:
110 * (U-Boot device node) (Physical Port)
111 * mmc0 (sd) USDHC2
112 * mmc1 (emmc) USDHC3
113 */
114 for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
115 switch (i) {
116 case 0:
117 init_clk_usdhc(1);
118 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
119 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
120 ARRAY_SIZE(usdhc2_pads));
121 gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset");
122 gpio_direction_output(USDHC2_RESET_GPIO, 0);
123 udelay(500);
124 gpio_direction_output(USDHC2_RESET_GPIO, 1);
125 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
126 gpio_direction_input(USDHC2_CD_GPIO);
127 break;
128 case 1:
129 init_clk_usdhc(2);
130 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
131 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
132 ARRAY_SIZE(usdhc3_pads));
133 break;
134 default:
135 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
136 i + 1);
137 return -EINVAL;
138 }
139
140 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
141 if (ret)
142 return ret;
143 }
144
145 return 0;
146 }
147
board_mmc_getcd(struct mmc * mmc)148 int board_mmc_getcd(struct mmc *mmc)
149 {
150 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
151 int ret = 0;
152
153 switch (cfg->esdhc_base) {
154 case USDHC2_BASE_ADDR:
155 ret = !gpio_get_value(USDHC2_CD_GPIO);
156 break;
157 case USDHC3_BASE_ADDR:
158 ret = 1;
159 break;
160 }
161
162 return ret;
163 }
164
165 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
166
167 static const iomux_v3_cfg_t wdog_pads[] = {
168 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
169 };
170
171 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
172
173 static const iomux_v3_cfg_t ser0_pads[] = {
174 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
175 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
176 };
177
board_early_init_f(void)178 int board_early_init_f(void)
179 {
180 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
181
182 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
183 set_wdog_reset(wdog);
184
185 imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads));
186
187 return 0;
188 }
189
190 static const iomux_v3_cfg_t reset_out_pad[] = {
191 MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19)
192 };
193
194 #define RESET_OUT_GPIO IMX_GPIO_NR(4, 27)
195
pulse_reset_out(void)196 static void pulse_reset_out(void)
197 {
198 imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad));
199
200 gpio_request(RESET_OUT_GPIO, "reset_out_gpio");
201 gpio_direction_output(RESET_OUT_GPIO, 0);
202 udelay(10);
203 gpio_direction_output(RESET_OUT_GPIO, 1);
204 }
205
206 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
207 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
208 struct i2c_pads_info i2c_dev_pads = {
209 .scl = {
210 .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC,
211 .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC,
212 .gp = IMX_GPIO_NR(3, 19),
213 },
214 .sda = {
215 .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC,
216 .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC,
217 .gp = IMX_GPIO_NR(3, 20),
218 },
219 };
220
power_init_board(void)221 int power_init_board(void)
222 {
223 struct udevice *dev;
224 int ret;
225
226 ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev);
227 if (ret) {
228 printf("Error: Failed to get PMIC\n");
229 return ret;
230 }
231
232 /* set VCC_DRAM (buck2) to 1.1V */
233 pmic_reg_write(dev, RN5T567_DC2DAC, 0x28);
234
235 /* set VCC_ARM (buck2) to 0.95V */
236 pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C);
237
238 return 0;
239 }
240
board_fit_config_name_match(const char * name)241 int board_fit_config_name_match(const char *name)
242 {
243 return 0;
244 }
245
board_init_f(ulong dummy)246 void board_init_f(ulong dummy)
247 {
248 int ret;
249
250 arch_cpu_init();
251
252 init_uart_clk(1);
253
254 board_early_init_f();
255
256 pulse_reset_out();
257
258 timer_init();
259
260 ret = spl_early_init();
261 if (ret) {
262 printf("Error: failed to initialize SPL!\n");
263 hang();
264 }
265
266 preloader_console_init();
267
268 enable_tzc380();
269
270 power_init_board();
271
272 spl_dram_init();
273 }
274