1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2021
4  * Phytium Technology Ltd <www.phytium.com>
5  * lixinde         <lixinde@phytium.com.cn>
6  * weichangzheng   <weichangzheng@phytium.com.cn>
7  */
8 
9 #ifndef _FT_POMELO_H
10 #define _FT_POMELO_H
11 
12 /* SMCCC ID */
13 #define CPU_SVC_VERSION			0xC2000F00
14 #define CPU_GET_RST_SOURCE		0xC2000F01
15 #define CPU_INIT_PLL			0xC2000F02
16 #define CPU_INIT_PCIE			0xC2000F03
17 #define CPU_INIT_MEM			0xC2000F04
18 #define CPU_INIT_SEC_SVC		0xC2000F05
19 
20 /*CPU RESET*/
21 #define CPU_RESET_POWER_ON		0x1
22 #define CPU_RESET_PLL			0x4
23 #define CPU_RESET_WATCH_DOG		0x8
24 
25 /* PLL */
26 #define PARAMETER_PLL_MAGIC		0x54460010
27 
28 /* PCIE */
29 #define PARAMETER_PCIE_MAGIC		0x54460011
30 #define CFG_INDEPENDENT_TREE		0x0
31 #define PCI_PEU0			0x1
32 #define PCI_PEU1			0x1
33 #define PEU1_OFFSET			16
34 #define PEU_C_OFFSET_MODE		16
35 #define PEU_C_OFFSET_SPEED		0
36 #define RC_MODE				0x1
37 #define X8X8				0x1
38 #define GEN3				3
39 
40 /* DDR */
41 #define PARAMETER_MCU_MAGIC		0x54460014
42 #define PARAM_MCU_VERSION		0x1
43 #define PARAM_MCU_SIZE			0x100
44 #define PARAM_CH_ENABLE			0x3
45 #define PARAM_ECC_ENABLE		0x3
46 #define PARAM_FORCE_SPD_DISABLE		0x0
47 #define PARAM_MCU_MISC_ENABLE		0x0
48 
49 #define UDIMM_TYPE			0x2
50 #define DIMM_X8				0x1
51 #define NO_MIRROR			0x0
52 #define NO_ECC_TYPE			0
53 #define DDR4_TYPE			0xC
54 
55 /* SEC */
56 #define PARAMETER_COMMON_MAGIC		0x54460013
57 
58 /* FLUSH L3 CASHE */
59 #define HNF_COUNT			0x8
60 #define HNF_PSTATE_REQ			(HNF_BASE + 0x10)
61 #define HNF_PSTATE_STAT			(HNF_BASE + 0x18)
62 #define HNF_PSTATE_OFF			0x0
63 #define HNF_PSTATE_SFONLY		0x1
64 #define HNF_PSTATE_HALF			0x2
65 #define HNF_PSTATE_FULL			0x3
66 #define HNF_STRIDE			0x10000
67 #define HNF_BASE			(unsigned long)(0x3A200000)
68 void ddr_init(void);
69 void sec_init(void);
70 void check_reset(void);
71 void pcie_init(void);
72 
73 #endif /* _FT_POMELO_H */
74