1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 * Copyright 2021 Purism
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <errno.h>
10 #include <asm/io.h>
11 #include <asm/arch/ddr.h>
12 #include <asm/arch/imx8mq_pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/clock.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/gpio.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <fsl_esdhc_imx.h>
20 #include <mmc.h>
21 #include <power/pmic.h>
22 #include <power/bd71837.h>
23 #include <hang.h>
24 #include <init.h>
25 #include <spl.h>
26 #include <usb.h>
27 #include <dwc3-uboot.h>
28 #include <linux/delay.h>
29 #include <linux/usb/gadget.h>
30 #include "librem5.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
spl_dram_init(void)34 void spl_dram_init(void)
35 {
36 /* ddr init */
37 if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
38 ddr_init(&dram_timing);
39 else
40 ddr_init(&dram_timing_b0);
41 }
42
spl_board_boot_device(enum boot_device boot_dev_spl)43 int spl_board_boot_device(enum boot_device boot_dev_spl)
44 {
45 log_debug("%s : starting\n", __func__);
46
47 switch (boot_dev_spl) {
48 case SD1_BOOT:
49 case MMC1_BOOT:
50 return BOOT_DEVICE_MMC1;
51 case USB_BOOT:
52 return BOOT_DEVICE_BOARD;
53 default:
54 return BOOT_DEVICE_NONE;
55 }
56 }
57
58 #define ECSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
59
60 static const iomux_v3_cfg_t ecspi_pads[] = {
61 IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
62 IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
63 IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
64 IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
65 };
66
board_ecspi_init(void)67 int board_ecspi_init(void)
68 {
69 imx_iomux_v3_setup_multiple_pads(ecspi_pads, ARRAY_SIZE(ecspi_pads));
70
71 return 0;
72 }
73
board_spi_cs_gpio(unsigned int bus,unsigned int cs)74 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
75 {
76 return (bus == 0 && cs == 0) ? (SPI1_SS0) : -1;
77 }
78
79 #define I2C_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | PAD_CTL_FSEL3)
80 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
81 struct i2c_pads_info i2c_pad_info1 = {
82 .scl = {
83 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
84 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
85 .gp = IMX_GPIO_NR(5, 14),
86 },
87 .sda = {
88 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
89 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
90 .gp = IMX_GPIO_NR(5, 15),
91 },
92 };
93
94 struct i2c_pads_info i2c_pad_info2 = {
95 .scl = {
96 .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC,
97 .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC,
98 .gp = IMX_GPIO_NR(5, 16),
99 },
100 .sda = {
101 .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC,
102 .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC,
103 .gp = IMX_GPIO_NR(5, 17),
104 },
105 };
106
107 struct i2c_pads_info i2c_pad_info3 = {
108 .scl = {
109 .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC,
110 .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC,
111 .gp = IMX_GPIO_NR(5, 18),
112 },
113 .sda = {
114 .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC,
115 .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC,
116 .gp = IMX_GPIO_NR(5, 19),
117 },
118 };
119
120 struct i2c_pads_info i2c_pad_info4 = {
121 .scl = {
122 .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | PC,
123 .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | PC,
124 .gp = IMX_GPIO_NR(5, 20),
125 },
126 .sda = {
127 .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | PC,
128 .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | PC,
129 .gp = IMX_GPIO_NR(5, 21),
130 },
131 };
132
133 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
134
135 static const iomux_v3_cfg_t uart_pads[] = {
136 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
137 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
138 IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
139 IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
140 IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
141 IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
142 IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
143 IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
144 };
145
146 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
147 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
148
board_mmc_getcd(struct mmc * mmc)149 int board_mmc_getcd(struct mmc *mmc)
150 {
151 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
152 int ret = 0;
153
154 switch (cfg->esdhc_base) {
155 case USDHC1_BASE_ADDR:
156 ret = 1;
157 break;
158 case USDHC2_BASE_ADDR:
159 ret = 1;
160 break;
161 }
162
163 return ret;
164 }
165
166 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
167 PAD_CTL_FSEL1)
168 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
169
170 static const iomux_v3_cfg_t usdhc1_pads[] = {
171 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
182 };
183
184 static const iomux_v3_cfg_t usdhc2_pads[] = {
185 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
186 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
187 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
188 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
189 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
190 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
191 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
192 };
193
194 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
195 {USDHC1_BASE_ADDR, 0, 8},
196 {USDHC2_BASE_ADDR, 0, 4},
197 };
198
board_mmc_init(struct bd_info * bis)199 int board_mmc_init(struct bd_info *bis)
200 {
201 int i, ret;
202 /*
203 * According to the board_mmc_init() the following map is done:
204 * (U-Boot device node) (Physical Port)
205 * mmc0 USDHC1
206 * mmc1 USDHC2
207 */
208 for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
209 log_debug("Initializing FSL USDHC port %d\n", i);
210 switch (i) {
211 case 0:
212 init_clk_usdhc(0);
213 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
214 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
215 ARRAY_SIZE(usdhc1_pads));
216 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
217 gpio_direction_output(USDHC1_PWR_GPIO, 0);
218 udelay(500);
219 gpio_direction_output(USDHC1_PWR_GPIO, 1);
220 break;
221 case 1:
222 init_clk_usdhc(1);
223 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
224 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
225 ARRAY_SIZE(usdhc2_pads));
226 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
227 gpio_direction_output(USDHC2_PWR_GPIO, 0);
228 udelay(500);
229 gpio_direction_output(USDHC2_PWR_GPIO, 1);
230 break;
231 default:
232 log_err("Warning: USDHC controller(%d) not supported\n", i + 1);
233 return -EINVAL;
234 }
235
236 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
237 if (ret)
238 return ret;
239 }
240
241 return 0;
242 }
243
244 #define LDO_VOLT_EN BIT(6)
245
246 /*
247 * Disable the charger - it will be re-enabled in u-boot
248 */
disable_charger_bq25895(void)249 void disable_charger_bq25895(void)
250 {
251 u8 val;
252 int timeout = 1000; // ms
253
254 /* Set the i2c bus */
255 i2c_set_bus_num(3);
256
257 /* disable ship mode if BATFET_DLY is set */
258 val = i2c_reg_read(0x6a, 0x09);
259 log_debug("REG09 0x%x\n", val);
260 if (val & 0x28) {
261 val = val & ~0x28;
262 i2c_reg_write(0x6a, 0x09, val);
263 }
264
265 /* disable and trigger DPDM, ICO, HVDCP and MaxCharge */
266 val = i2c_reg_read(0x6a, 0x02);
267 log_debug("REG02 0x%x\n", val);
268 val &= 0xe0;
269 i2c_reg_write(0x6a, 0x02, val);
270
271 /* disable charger and enable BAT_LOADEN */
272 val = i2c_reg_read(0x6a, 0x03);
273 log_debug("REG03 0x%x\n", val);
274 val = (val | 0x80) & ~0x10;
275 i2c_reg_write(0x6a, 0x03, val);
276
277 mdelay(10);
278
279 /* force ADC conversions */
280 val = i2c_reg_read(0x6a, 0x02);
281 log_debug("REG02 0x%x\n", val);
282 val = (val | 0x80) & ~0x40;
283 i2c_reg_write(0x6a, 0x02, val);
284
285 do {
286 mdelay(10);
287 timeout -= 10;
288 } while ((i2c_reg_read(0x6a, 0x02) & 0x80) && (timeout > 0));
289
290 /* enable STAT pin */
291 val = i2c_reg_read(0x6a, 0x07);
292 log_debug("REG07 0x%x\n", val);
293 val = val & ~0x40;
294 i2c_reg_write(0x6a, 0x07, val);
295
296 /* check VBUS */
297 val = i2c_reg_read(0x6a, 0x11);
298 log_debug("VBUS good %d\n", (val >> 7) & 1);
299 log_debug("VBUS mV %d\n", (val & 0x7f) * 100 + 2600);
300
301 /* check VBAT */
302 val = i2c_reg_read(0x6a, 0x0e);
303 log_debug("VBAT mV %d\n", (val & 0x7f) * 20 + 2304);
304
305 /* limit the VINDPM to 3.9V */
306 i2c_reg_write(0x6a, 0x0d, 0x8d);
307
308 /* set the max voltage to 4.192V */
309 val = i2c_reg_read(0x6a, 0x6);
310 val = (val & ~0xFC) | 0x16 << 2;
311 i2c_reg_write(0x6a, 0x6, val);
312
313 /* set the SYS_MIN to 3.7V */
314 val = i2c_reg_read(0x6a, 0x3);
315 val = val | 0xE;
316 i2c_reg_write(0x6a, 0x3, val);
317
318 /* disable BAT_LOADEN */
319 val = i2c_reg_read(0x6a, 0x03);
320 log_debug("REG03 0x%x\n", val);
321 val = val & ~0x80;
322 i2c_reg_write(0x6a, 0x03, val);
323 }
324
325 #define I2C_PMIC 0
326 #define POWER_BD71837_I2C_BUS 0
327 #define POWER_BD71837_I2C_ADDR 0x4B
328
power_bd71837_init(unsigned char bus)329 int power_bd71837_init(unsigned char bus)
330 {
331 static const char name[] = BD718XX_REGULATOR_DRIVER;
332 struct pmic *p = pmic_alloc();
333
334 if (!p) {
335 log_err("%s: POWER allocation error!\n", __func__);
336 return -ENOMEM;
337 }
338
339 p->name = name;
340 p->interface = I2C_PMIC;
341 p->number_of_regs = BD718XX_MAX_REGISTER;
342 p->hw.i2c.addr = POWER_BD71837_I2C_ADDR;
343 p->hw.i2c.tx_num = 1;
344 p->bus = bus;
345
346 return 0;
347 }
348
power_init_board(void)349 int power_init_board(void)
350 {
351 struct pmic *p;
352 int ldo[] = {BD718XX_LDO5_VOLT, BD718XX_LDO6_VOLT,
353 BD71837_LDO7_VOLT};
354 u32 val;
355 int i, rv;
356
357 /* Set the i2c bus */
358 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
359
360 /*
361 * Init PMIC
362 */
363 rv = power_bd71837_init(POWER_BD71837_I2C_BUS);
364 if (rv) {
365 log_err("%s: power_bd71837_init(%d) error %d\n", __func__,
366 POWER_BD71837_I2C_BUS, rv);
367 goto out;
368 }
369
370 p = pmic_get(BD718XX_REGULATOR_DRIVER);
371 if (!p) {
372 log_err("%s: pmic_get(%s) failed\n", __func__, BD718XX_REGULATOR_DRIVER);
373 rv = -ENODEV;
374 goto out;
375 }
376
377 rv = pmic_probe(p);
378 if (rv) {
379 log_err("%s: pmic_probe() error %d\n", __func__, rv);
380 goto out;
381 }
382
383 /*
384 * Unlock all regs
385 */
386 pmic_reg_write(p, BD718XX_REGLOCK, 0);
387
388 /* find the reset cause */
389 pmic_reg_read(p, 0x29, &val);
390 log_debug("%s: reset cause %d\n", __func__, val);
391
392 /*
393 * Reconfigure default voltages and disable:
394 * - BUCK3: VDD_GPU_0V9 (1.00 -> 0.90)
395 * - BUCK4: VDD_VPU_0V9 (1.00 -> 0.90)
396 */
397 pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
398 pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
399
400 /*
401 * Enable PHYs voltages: LDO5-7
402 */
403 for (i = 0; i < ARRAY_SIZE(ldo); i++) {
404 rv = pmic_reg_read(p, ldo[i], &val);
405 if (rv) {
406 log_err("%s: pmic_read(%x) error %d\n", __func__,
407 ldo[i], rv);
408 continue;
409 }
410
411 pmic_reg_write(p, ldo[i], val | LDO_VOLT_EN);
412 }
413
414 udelay(500);
415
416 rv = 0;
417 out:
418 return rv;
419 }
420
usb_gadget_handle_interrupts(int index)421 int usb_gadget_handle_interrupts(int index)
422 {
423 dwc3_uboot_handle_interrupt(0);
424 return 0;
425 }
426
dwc3_nxp_usb_phy_init(struct dwc3_device * dwc3)427 static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
428 {
429 u32 RegData;
430
431 RegData = readl(dwc3->base + USB_PHY_CTRL1);
432 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
433 USB_PHY_CTRL1_COMMONONN);
434 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
435 writel(RegData, dwc3->base + USB_PHY_CTRL1);
436
437 RegData = readl(dwc3->base + USB_PHY_CTRL0);
438 RegData |= USB_PHY_CTRL0_REF_SSP_EN;
439 RegData &= ~USB_PHY_CTRL0_SSC_RANGE_MASK;
440 RegData |= USB_PHY_CTRL0_SSC_RANGE_4003PPM;
441 writel(RegData, dwc3->base + USB_PHY_CTRL0);
442
443 RegData = readl(dwc3->base + USB_PHY_CTRL2);
444 RegData |= USB_PHY_CTRL2_TXENABLEN0;
445 writel(RegData, dwc3->base + USB_PHY_CTRL2);
446
447 RegData = readl(dwc3->base + USB_PHY_CTRL1);
448 RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
449 writel(RegData, dwc3->base + USB_PHY_CTRL1);
450
451 /* Disable rx term override */
452 RegData = readl(dwc3->base + USB_PHY_CTRL6);
453 RegData &= ~USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
454 writel(RegData, dwc3->base + USB_PHY_CTRL6);
455 }
456
457 static struct dwc3_device dwc3_device0_data = {
458 .maximum_speed = USB_SPEED_HIGH,
459 .base = USB1_BASE_ADDR,
460 .dr_mode = USB_DR_MODE_PERIPHERAL,
461 .index = 0,
462 };
463
464 static struct dwc3_device dwc3_device1_data = {
465 .maximum_speed = USB_SPEED_HIGH,
466 .base = USB2_BASE_ADDR,
467 .dr_mode = USB_DR_MODE_HOST,
468 .index = 1,
469 };
470
board_usb_init(int index,enum usb_init_type init)471 int board_usb_init(int index, enum usb_init_type init)
472 {
473 int ret = 0;
474
475 printf("%s : index %d type %d\n", __func__, index, init);
476
477 if (index == 0 && init == USB_INIT_DEVICE) {
478 dwc3_nxp_usb_phy_init(&dwc3_device0_data);
479 ret = dwc3_uboot_init(&dwc3_device0_data);
480 }
481 if (index == 1 && init == USB_INIT_HOST) {
482 dwc3_nxp_usb_phy_init(&dwc3_device1_data);
483 ret = dwc3_uboot_init(&dwc3_device1_data);
484 }
485
486 return ret;
487 }
488
board_usb_cleanup(int index,enum usb_init_type init)489 int board_usb_cleanup(int index, enum usb_init_type init)
490 {
491 u32 RegData;
492 struct dwc3_device *dwc3;
493
494 printf("%s : %d\n", __func__, index);
495
496 if (index == 0 && init == USB_INIT_DEVICE)
497 dwc3 = &dwc3_device0_data;
498 if (index == 1 && init == USB_INIT_HOST)
499 dwc3 = &dwc3_device1_data;
500
501 dwc3_uboot_exit(index);
502
503 /* reset the phy */
504 RegData = readl(dwc3->base + USB_PHY_CTRL1);
505 RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
506 USB_PHY_CTRL1_COMMONONN);
507 RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
508 writel(RegData, dwc3->base + USB_PHY_CTRL1);
509
510 /* enable rx term override */
511 RegData = readl(dwc3->base + USB_PHY_CTRL6);
512 RegData |= USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
513 writel(RegData, dwc3->base + USB_PHY_CTRL6);
514
515 return 0;
516 }
517
spl_board_init(void)518 void spl_board_init(void)
519 {
520 if (is_usb_boot())
521 puts("USB Boot\n");
522 else
523 puts("Normal Boot\n");
524 }
525
board_boot_order(u32 * spl_boot_list)526 void board_boot_order(u32 *spl_boot_list)
527 {
528 if (is_usb_boot())
529 spl_boot_list[0] = BOOT_DEVICE_BOARD;
530 else
531 spl_boot_list[0] = BOOT_DEVICE_MMC1;
532 }
533
534 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
535
536 static const iomux_v3_cfg_t wdog_pads[] = {
537 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
538 };
539
board_init_f(ulong dummy)540 void board_init_f(ulong dummy)
541 {
542 int ret;
543 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
544
545 arch_cpu_init();
546
547 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
548 set_wdog_reset(wdog);
549
550 init_uart_clk(CONSOLE_UART_CLK);
551 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
552
553 #ifdef CONSOLE_ON_UART4
554 gpio_request(WIFI_EN, "WIFI_EN");
555 gpio_direction_output(WIFI_EN, 1);
556 #endif
557
558 board_early_init_f();
559
560 timer_init();
561
562 preloader_console_init();
563
564 ret = spl_init();
565 if (ret) {
566 log_err("spl_init() failed: %d\n", ret);
567 hang();
568 }
569
570 enable_tzc380();
571
572 printf("Initializing pinmux\n");
573 init_pinmux();
574 gpio_direction_output(LED_G, 1);
575 gpio_direction_output(MOTO, 1);
576 mdelay(50);
577 gpio_direction_output(MOTO, 0);
578
579 /* Enable and configure i2c buses not used below */
580 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
581 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
582 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
583
584 power_init_board();
585
586 disable_charger_bq25895();
587
588 /* initialize this for M4 even if u-boot doesn't have SF_CMD */
589 printf("Initializing ECSPI\n");
590 board_ecspi_init();
591
592 /* DDR initialization */
593 printf("Initializing DRAM\n");
594 spl_dram_init();
595 }
596