1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/gose/gose.c
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 */
7
8 #include <common.h>
9 #include <clock_legacy.h>
10 #include <cpu_func.h>
11 #include <env.h>
12 #include <hang.h>
13 #include <init.h>
14 #include <malloc.h>
15 #include <dm.h>
16 #include <asm/global_data.h>
17 #include <dm/platform_data/serial_sh.h>
18 #include <env_internal.h>
19 #include <asm/processor.h>
20 #include <asm/mach-types.h>
21 #include <asm/io.h>
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/gpio.h>
27 #include <asm/arch/rmobile.h>
28 #include <asm/arch/rcar-mstp.h>
29 #include <asm/arch/sh_sdhi.h>
30 #include <netdev.h>
31 #include <miiphy.h>
32 #include <i2c.h>
33 #include "qos.h"
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)38 void s_init(void)
39 {
40 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
41 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
42 u32 stc;
43
44 /* Watchdog init */
45 writel(0xA5A5A500, &rwdt->rwtcsra);
46 writel(0xA5A5A500, &swdt->swtcsra);
47
48 /* CPU frequency setting. Set to 1.5GHz */
49 stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
50 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
51
52 /* QoS */
53 qos_init();
54 }
55
56 #define TMU0_MSTP125 BIT(25)
57
58 #define SD1CKCR 0xE6150078
59 #define SD2CKCR 0xE615026C
60 #define SD_97500KHZ 0x7
61
board_early_init_f(void)62 int board_early_init_f(void)
63 {
64 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
65
66 /*
67 * SD0 clock is set to 97.5MHz by default.
68 * Set SD1 and SD2 to the 97.5MHz as well.
69 */
70 writel(SD_97500KHZ, SD1CKCR);
71 writel(SD_97500KHZ, SD2CKCR);
72
73 return 0;
74 }
75
76 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
77
board_init(void)78 int board_init(void)
79 {
80 /* adress of boot parameters */
81 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
82
83 /* Force ethernet PHY out of reset */
84 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
85 gpio_direction_output(ETHERNET_PHY_RESET, 0);
86 mdelay(10);
87 gpio_direction_output(ETHERNET_PHY_RESET, 1);
88
89 return 0;
90 }
91
dram_init(void)92 int dram_init(void)
93 {
94 if (fdtdec_setup_mem_size_base() != 0)
95 return -EINVAL;
96
97 return 0;
98 }
99
dram_init_banksize(void)100 int dram_init_banksize(void)
101 {
102 fdtdec_setup_memory_banksize();
103
104 return 0;
105 }
106
107 /* KSZ8041RNLI */
108 #define PHY_CONTROL1 0x1E
109 #define PHY_LED_MODE 0xC000
110 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)111 int board_phy_config(struct phy_device *phydev)
112 {
113 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
114 ret &= ~PHY_LED_MODE;
115 ret |= PHY_LED_MODE_ACK;
116 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
117
118 return 0;
119 }
120
reset_cpu(void)121 void reset_cpu(void)
122 {
123 struct udevice *dev;
124 const u8 pmic_bus = 6;
125 const u8 pmic_addr = 0x58;
126 u8 data;
127 int ret;
128
129 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
130 if (ret)
131 hang();
132
133 ret = dm_i2c_read(dev, 0x13, &data, 1);
134 if (ret)
135 hang();
136
137 data |= BIT(1);
138
139 ret = dm_i2c_write(dev, 0x13, &data, 1);
140 if (ret)
141 hang();
142 }
143
env_get_location(enum env_operation op,int prio)144 enum env_location env_get_location(enum env_operation op, int prio)
145 {
146 const u32 load_magic = 0xb33fc0de;
147
148 /* Block environment access if loaded using JTAG */
149 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
150 (op != ENVOP_INIT))
151 return ENVL_UNKNOWN;
152
153 if (prio)
154 return ENVL_UNKNOWN;
155
156 return ENVL_SPI_FLASH;
157 }
158