1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2017 Renesas Electronics
4 * Copyright (C) 2017 Chris Brandt
5 */
6#include <config.h>
7#include <asm/macro.h>
8
9/* Watchdog Registers */
10#define RZA1_WDT_BASE	0xFCFE0000
11#define WTCSR	(RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
12#define WTCNT	(RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
13#define WRCSR	(RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
14
15/* Standby controller registers (chapter 55) */
16#define RZA1_STBCR_BASE	0xFCFE0020
17#define STBCR1	(RZA1_STBCR_BASE + 0x00)
18#define STBCR2	(RZA1_STBCR_BASE + 0x04)
19#define STBCR3	(RZA1_STBCR_BASE + 0x400)
20#define STBCR4	(RZA1_STBCR_BASE + 0x404)
21#define STBCR5	(RZA1_STBCR_BASE + 0x408)
22#define STBCR6	(RZA1_STBCR_BASE + 0x40c)
23#define STBCR7	(RZA1_STBCR_BASE + 0x410)
24#define STBCR8	(RZA1_STBCR_BASE + 0x414)
25#define STBCR9	(RZA1_STBCR_BASE + 0x418)
26#define STBCR10	(RZA1_STBCR_BASE + 0x41c)
27#define STBCR11	(RZA1_STBCR_BASE + 0x420)
28#define STBCR12	(RZA1_STBCR_BASE + 0x424)
29#define STBCR13	(RZA1_STBCR_BASE + 0x450)
30
31/* Clock Registers */
32#define RZA1_FRQCR_BASE	0xFCFE0010
33#define FRQCR	(RZA1_FRQCR_BASE + 0x00)
34#define FRQCR2	(RZA1_FRQCR_BASE + 0x04)
35
36#define SYSCR1	0xFCFE0400 /* System control register 1 */
37#define SYSCR2	0xFCFE0404 /* System control register 2 */
38#define SYSCR3	0xFCFE0408 /* System control register 3 */
39
40/* Disable WDT */
41#define WTCSR_D		0xA518
42#define WTCNT_D		0x5A00
43
44/* Enable all peripheral clocks */
45#define STBCR3_D	0x00000000
46#define STBCR4_D	0x00000000
47#define STBCR5_D	0x00000000
48#define STBCR6_D	0x00000000
49#define STBCR7_D	0x00000024
50#define STBCR8_D	0x00000005
51#define STBCR9_D	0x00000000
52#define STBCR10_D	0x00000000
53#define STBCR11_D	0x000000c0
54#define STBCR12_D	0x000000f0
55
56/*
57 * Set all system clocks to full speed.
58 * On reset, the CPU will be running at 1/2 speed.
59 * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
60 */
61#define FRQCR_D		0x0035
62#define FRQCR2_D	0x0001
63
64	.global	lowlevel_init
65
66	.text
67	.align	2
68
69lowlevel_init:
70	/* PL310 init */
71	write32 0x3fffff80, 0x00000001
72
73	/* Disable WDT */
74	write16	WTCSR, WTCSR_D
75	write16	WTCNT, WTCNT_D
76
77	/* Set clocks */
78	write16	FRQCR, FRQCR_D
79	write16	FRQCR2, FRQCR2_D
80
81	/* Enable all peripherals(Standby Control) */
82	write8 STBCR3, STBCR3_D
83	write8 STBCR4, STBCR4_D
84	write8 STBCR5, STBCR5_D
85	write8 STBCR6, STBCR6_D
86	write8 STBCR7, STBCR7_D
87	write8 STBCR8, STBCR8_D
88	write8 STBCR9, STBCR9_D
89	write8 STBCR10, STBCR10_D
90	write8 STBCR11, STBCR11_D
91	write8 STBCR12, STBCR12_D
92
93	/* For serial booting, enable read ahead caching to speed things up */
94#define DRCR_0  0x3FEFA00C
95	write32 DRCR_0, 0x00010100	/* Read Burst ON, Length=2 */
96
97	/* Enable all internal RAM */
98	write8 SYSCR1, 0xFF
99	write8 SYSCR2, 0xFF
100	write8 SYSCR3, 0xFF
101
102	nop
103	/* back to arch calling code */
104	mov	pc, lr
105
106	.align 4
107