1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/koelsch/koelsch.c
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 *
7 */
8
9 #include <common.h>
10 #include <clock_legacy.h>
11 #include <cpu_func.h>
12 #include <env.h>
13 #include <hang.h>
14 #include <init.h>
15 #include <malloc.h>
16 #include <dm.h>
17 #include <asm/global_data.h>
18 #include <dm/platform_data/serial_sh.h>
19 #include <env_internal.h>
20 #include <asm/processor.h>
21 #include <asm/mach-types.h>
22 #include <asm/io.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/gpio.h>
28 #include <asm/arch/rmobile.h>
29 #include <asm/arch/rcar-mstp.h>
30 #include <asm/arch/sh_sdhi.h>
31 #include <netdev.h>
32 #include <miiphy.h>
33 #include <i2c.h>
34 #include <div64.h>
35 #include "qos.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)40 void s_init(void)
41 {
42 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
43 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
44 u32 stc;
45
46 /* Watchdog init */
47 writel(0xA5A5A500, &rwdt->rwtcsra);
48 writel(0xA5A5A500, &swdt->swtcsra);
49
50 /* CPU frequency setting. Set to 1.5GHz */
51 stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
52 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
53
54 /* QoS */
55 qos_init();
56 }
57
58 #define TMU0_MSTP125 BIT(25)
59
60 #define SD1CKCR 0xE6150078
61 #define SD2CKCR 0xE615026C
62 #define SD_97500KHZ 0x7
63
board_early_init_f(void)64 int board_early_init_f(void)
65 {
66 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
67
68 /*
69 * SD0 clock is set to 97.5MHz by default.
70 * Set SD1 and SD2 to the 97.5MHz as well.
71 */
72 writel(SD_97500KHZ, SD1CKCR);
73 writel(SD_97500KHZ, SD2CKCR);
74
75 return 0;
76 }
77
78 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
79
board_init(void)80 int board_init(void)
81 {
82 /* adress of boot parameters */
83 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
84
85 /* Force ethernet PHY out of reset */
86 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
87 gpio_direction_output(ETHERNET_PHY_RESET, 0);
88 mdelay(10);
89 gpio_direction_output(ETHERNET_PHY_RESET, 1);
90
91 return 0;
92 }
93
dram_init(void)94 int dram_init(void)
95 {
96 if (fdtdec_setup_mem_size_base() != 0)
97 return -EINVAL;
98
99 return 0;
100 }
101
dram_init_banksize(void)102 int dram_init_banksize(void)
103 {
104 fdtdec_setup_memory_banksize();
105
106 return 0;
107 }
108
109 /* Koelsch has KSZ8041NL/RNL */
110 #define PHY_CONTROL1 0x1E
111 #define PHY_LED_MODE 0xC000
112 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)113 int board_phy_config(struct phy_device *phydev)
114 {
115 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
116 ret &= ~PHY_LED_MODE;
117 ret |= PHY_LED_MODE_ACK;
118 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
119
120 return 0;
121 }
122
reset_cpu(void)123 void reset_cpu(void)
124 {
125 struct udevice *dev;
126 const u8 pmic_bus = 6;
127 const u8 pmic_addr = 0x58;
128 u8 data;
129 int ret;
130
131 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
132 if (ret)
133 hang();
134
135 ret = dm_i2c_read(dev, 0x13, &data, 1);
136 if (ret)
137 hang();
138
139 data |= BIT(1);
140
141 ret = dm_i2c_write(dev, 0x13, &data, 1);
142 if (ret)
143 hang();
144 }
145
env_get_location(enum env_operation op,int prio)146 enum env_location env_get_location(enum env_operation op, int prio)
147 {
148 const u32 load_magic = 0xb33fc0de;
149
150 /* Block environment access if loaded using JTAG */
151 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
152 (op != ENVOP_INIT))
153 return ENVL_UNKNOWN;
154
155 if (prio)
156 return ENVL_UNKNOWN;
157
158 return ENVL_SPI_FLASH;
159 }
160