1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/stout/stout.c
4 * This file is Stout board support.
5 *
6 * Copyright (C) 2015 Renesas Electronics Europe GmbH
7 * Copyright (C) 2015 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.
9 */
10
11 #include <common.h>
12 #include <clock_legacy.h>
13 #include <env.h>
14 #include <init.h>
15 #include <malloc.h>
16 #include <netdev.h>
17 #include <dm.h>
18 #include <asm/global_data.h>
19 #include <dm/platform_data/serial_sh.h>
20 #include <env_internal.h>
21 #include <asm/processor.h>
22 #include <asm/mach-types.h>
23 #include <asm/io.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/errno.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/gpio.h>
29 #include <asm/arch/rmobile.h>
30 #include <asm/arch/rcar-mstp.h>
31 #include <asm/arch/mmc.h>
32 #include <asm/arch/sh_sdhi.h>
33 #include <miiphy.h>
34 #include <i2c.h>
35 #include <mmc.h>
36 #include "qos.h"
37 #include "cpld.h"
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)42 void s_init(void)
43 {
44 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
45 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
46
47 /* Watchdog init */
48 writel(0xA5A5A500, &rwdt->rwtcsra);
49 writel(0xA5A5A500, &swdt->swtcsra);
50
51 /* CPU frequency setting. Set to 1.4GHz */
52 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
53 u32 stat = 0;
54 u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
55 << PLL0_STC_BIT;
56 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
57
58 do {
59 stat = readl(PLLECR) & PLL0ST;
60 } while (stat == 0x0);
61 }
62
63 /* QoS(Quality-of-Service) Init */
64 qos_init();
65 }
66
67 #define TMU0_MSTP125 BIT(25)
68
69 #define SD2CKCR 0xE6150078
70 #define SD2_97500KHZ 0x7
71
board_early_init_f(void)72 int board_early_init_f(void)
73 {
74 /* TMU0 */
75 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
76
77 /*
78 * SD0 clock is set to 97.5MHz by default.
79 * Set SD2 to the 97.5MHz as well.
80 */
81 writel(SD2_97500KHZ, SD2CKCR);
82
83 return 0;
84 }
85
86 #define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
87
board_init(void)88 int board_init(void)
89 {
90 /* adress of boot parameters */
91 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
92
93 cpld_init();
94
95 /* Force ethernet PHY out of reset */
96 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
97 gpio_direction_output(ETHERNET_PHY_RESET, 0);
98 mdelay(20);
99 gpio_direction_output(ETHERNET_PHY_RESET, 1);
100
101 return 0;
102 }
103
dram_init(void)104 int dram_init(void)
105 {
106 if (fdtdec_setup_mem_size_base() != 0)
107 return -EINVAL;
108
109 return 0;
110 }
111
dram_init_banksize(void)112 int dram_init_banksize(void)
113 {
114 fdtdec_setup_memory_banksize();
115
116 return 0;
117 }
118
119 /* Stout has KSZ8041NL/RNL */
120 #define PHY_CONTROL1 0x1E
121 #define PHY_LED_MODE 0xC000
122 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)123 int board_phy_config(struct phy_device *phydev)
124 {
125 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
126 ret &= ~PHY_LED_MODE;
127 ret |= PHY_LED_MODE_ACK;
128 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
129
130 return 0;
131 }
132
env_get_location(enum env_operation op,int prio)133 enum env_location env_get_location(enum env_operation op, int prio)
134 {
135 const u32 load_magic = 0xb33fc0de;
136
137 /* Block environment access if loaded using JTAG */
138 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
139 (op != ENVOP_INIT))
140 return ENVL_UNKNOWN;
141
142 if (prio)
143 return ENVL_UNKNOWN;
144
145 return ENVL_SPI_FLASH;
146 }
147