1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2007-2008
4  * Stelian Pop <stelian@popies.net>
5  * Lead Tech Design <www.leadtechdesign.com>
6  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
7  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8  */
9 
10 #include <common.h>
11 #include <init.h>
12 #include <asm/global_data.h>
13 #include <linux/sizes.h>
14 #include <asm/io.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_matrix.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/mach-types.h>
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 /* ------------------------------------------------------------------------- */
27 /*
28  * Miscellaneous platform dependent initializations
29  */
30 
31 #ifdef CONFIG_CMD_NAND
pm9263_nand_hw_init(void)32 static void pm9263_nand_hw_init(void)
33 {
34 	unsigned long csa;
35 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
36 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
37 
38 	/* Enable CS3 */
39 	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
40 	writel(csa, &matrix->csa[0]);
41 
42 	/* Configure SMC CS3 for NAND/SmartMedia */
43 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
44 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
45 		&smc->cs[3].setup);
46 
47 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
48 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
49 		&smc->cs[3].pulse);
50 
51 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
52 		&smc->cs[3].cycle);
53 
54 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 		AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 		AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
59 		AT91_SMC_MODE_DBW_8 |
60 #endif
61 		AT91_SMC_MODE_TDF_CYCLE(2),
62 		&smc->cs[3].mode);
63 
64 	/* Configure RDY/BSY */
65 	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
66 
67 	/* Enable NandFlash */
68 	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
69 }
70 #endif
71 
board_early_init_f(void)72 int board_early_init_f(void)
73 {
74 	return 0;
75 }
76 
board_init(void)77 int board_init(void)
78 {
79 	/* arch number of PM9263 Board */
80 	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
81 
82 	/* address of boot parameters */
83 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
84 
85 #ifdef CONFIG_CMD_NAND
86 	pm9263_nand_hw_init();
87 #endif
88 #ifdef CONFIG_USB_OHCI_NEW
89 	at91_uhp_hw_init();
90 #endif
91 	return 0;
92 }
93 
dram_init(void)94 int dram_init(void)
95 {
96 	/* dram_init must store complete RAM size in gd->ram_size */
97 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
98 				PHYS_SDRAM_SIZE);
99 	return 0;
100 }
101 
dram_init_banksize(void)102 int dram_init_banksize(void)
103 {
104 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
105 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
106 
107 	return 0;
108 }
109 
110 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)111 int checkboard (void)
112 {
113 	char *ss;
114 
115 	printf ("Board : Ronetix PM9263\n");
116 
117 	switch (gd->fb_base) {
118 	case PHYS_PSRAM:
119 		ss = "(PSRAM)";
120 		break;
121 
122 	case ATMEL_BASE_SRAM0:
123 		ss = "(Internal SRAM)";
124 		break;
125 
126 	default:
127 		ss = "";
128 		break;
129 	}
130 	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
131 
132 	printf ("\n");
133 	return 0;
134 }
135 #endif
136