1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * u-boot/board/socionext/developerbox/developerbox.c
4 *
5 * Copyright (C) 2016-2017 Socionext Inc.
6 * Copyright (C) 2021 Linaro Ltd.
7 */
8 #include <asm/types.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <common.h>
13 #include <efi.h>
14 #include <efi_loader.h>
15 #include <env_internal.h>
16 #include <fdt_support.h>
17 #include <log.h>
18
19 #include <linux/kernel.h>
20
21 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
22 struct efi_fw_image fw_images[] = {
23 {
24 .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
25 .fw_name = u"DEVELOPERBOX-UBOOT",
26 .image_index = 1,
27 },
28 {
29 .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
30 .fw_name = u"DEVELOPERBOX-FIP",
31 .image_index = 2,
32 },
33 {
34 .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID,
35 .fw_name = u"DEVELOPERBOX-OPTEE",
36 .image_index = 3,
37 },
38 };
39
40 struct efi_capsule_update_info update_info = {
41 .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;"
42 "fip.bin raw 180000 78000;"
43 "optee.bin raw 500000 100000",
44 .images = fw_images,
45 };
46
47 u8 num_image_type_guids = ARRAY_SIZE(fw_images);
48 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
49
50 static struct mm_region sc2a11_mem_map[] = {
51 {
52 .virt = 0x0UL,
53 .phys = 0x0UL,
54 .size = 0x80000000UL,
55 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56 PTE_BLOCK_OUTER_SHARE
57 }, {
58 /* 1st DDR block */
59 .virt = 0x80000000UL,
60 .phys = 0x80000000UL,
61 .size = PHYS_SDRAM_SIZE,
62 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
63 PTE_BLOCK_OUTER_SHARE
64 }, {
65 /* 2nd DDR place holder */
66 0,
67 }, {
68 /* 3rd DDR place holder */
69 0,
70 }, {
71 /* List terminator */
72 0,
73 }
74 };
75
76 struct mm_region *mem_map = sc2a11_mem_map;
77
78 #define DDR_REGION_INDEX(i) (1 + (i))
79 #define MAX_DDR_REGIONS 3
80
81 struct draminfo_entry {
82 u64 base;
83 u64 size;
84 };
85
86 struct draminfo {
87 u32 nr_regions;
88 u32 reserved;
89 struct draminfo_entry entry[3];
90 };
91
92 DECLARE_GLOBAL_DATA_PTR;
93
94 #define LOAD_OFFSET 0x100
95
96 /* SCBM System MMU is used for eMMC and NETSEC */
97 #define SCBM_SMMU_ADDR (0x52e00000UL)
98 #define SMMU_SCR0_OFFS (0x0)
99 #define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
100 #define SMMU_SCR0_MTCFG (0x1 << 20)
101 #define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
102
synquacer_setup_scbm_smmu(void)103 static void synquacer_setup_scbm_smmu(void)
104 {
105 writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
106 SCBM_SMMU_ADDR + SMMU_SCR0_OFFS);
107 }
108
109 /*
110 * Miscellaneous platform dependent initialisations
111 */
board_init(void)112 int board_init(void)
113 {
114 gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
115
116 gd->env_addr = (ulong)&default_environment[0];
117
118 synquacer_setup_scbm_smmu();
119
120 return 0;
121 }
122
ft_board_setup(void * blob,struct bd_info * bd)123 int ft_board_setup(void *blob, struct bd_info *bd)
124 {
125 /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
126 fdt_del_node_and_alias(blob, "spi_nor");
127 fdt_del_node_and_alias(blob, "i2c0");
128
129 return 0;
130 }
131
132 /*
133 * DRAM configuration
134 */
135
dram_init(void)136 int dram_init(void)
137 {
138 struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
139 struct draminfo_entry *ent = synquacer_draminfo->entry;
140
141 gd->ram_size = ent[0].size;
142 gd->ram_base = ent[0].base;
143
144 return 0;
145 }
146
dram_init_banksize(void)147 int dram_init_banksize(void)
148 {
149 struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
150 struct draminfo_entry *ent = synquacer_draminfo->entry;
151 int i;
152
153 for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
154 if (i < synquacer_draminfo->nr_regions) {
155 debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
156 gd->bd->bi_dram[i].start = ent[i].base;
157 gd->bd->bi_dram[i].size = ent[i].size;
158 }
159 }
160
161 return 0;
162 }
163
build_mem_map(void)164 void build_mem_map(void)
165 {
166 struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
167 struct draminfo_entry *ent = synquacer_draminfo->entry;
168 struct mm_region *mr;
169 int i, ri;
170
171 if (synquacer_draminfo->nr_regions < 1) {
172 log_err("Failed to get correct DRAM information\n");
173 return;
174 }
175
176 /* Update memory region maps */
177 for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
178 if (i >= MAX_DDR_REGIONS)
179 break;
180
181 ri = DDR_REGION_INDEX(i);
182 mem_map[ri].phys = ent[i].base;
183 mem_map[ri].size = ent[i].size;
184 mem_map[ri].virt = mem_map[ri].phys;
185 if (i == 0)
186 continue;
187
188 mr = &mem_map[DDR_REGION_INDEX(0)];
189 mem_map[ri].attrs = mr->attrs;
190 }
191 }
192
enable_caches(void)193 void enable_caches(void)
194 {
195 build_mem_map();
196
197 icache_enable();
198 dcache_enable();
199 }
200
print_cpuinfo(void)201 int print_cpuinfo(void)
202 {
203 printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
204 return 0;
205 }
206