1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
7 #include <common.h>
8 #include <asm/arch/regs.h>
9 #include <asm/arch/spl.h>
10 #include <asm/io.h>
11 #include <log.h>
12 #include <spl.h>
13
14 #define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
15 #define JH7110_CLK_CPU_ROOT_SHIFT 24
16 #define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
17
spl_board_init_f(void)18 int spl_board_init_f(void)
19 {
20 int ret;
21
22 ret = spl_soc_init();
23 if (ret) {
24 debug("JH7110 SPL init failed: %d\n", ret);
25 return ret;
26 }
27
28 return 0;
29 }
30
spl_boot_device(void)31 u32 spl_boot_device(void)
32 {
33 u32 mode;
34
35 mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
36 & JH7110_BOOT_MODE_SELECT_MASK;
37 switch (mode) {
38 case 0:
39 return BOOT_DEVICE_SPI;
40
41 case 1:
42 return BOOT_DEVICE_MMC2;
43
44 case 2:
45 return BOOT_DEVICE_MMC1;
46
47 case 3:
48 return BOOT_DEVICE_UART;
49
50 default:
51 debug("Unsupported boot device 0x%x.\n", mode);
52 return BOOT_DEVICE_NONE;
53 }
54 }
55
board_init_f(ulong dummy)56 void board_init_f(ulong dummy)
57 {
58 int ret;
59
60 ret = spl_early_init();
61 if (ret)
62 panic("spl_early_init() failed: %d\n", ret);
63
64 riscv_cpu_setup(NULL, NULL);
65 preloader_console_init();
66
67 /* Set the parent clock of cpu_root clock to pll0,
68 * it must be initialized here
69 */
70 clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
71 JH7110_CLK_CPU_ROOT_MASK,
72 BIT(JH7110_CLK_CPU_ROOT_SHIFT));
73
74 ret = spl_board_init_f();
75 if (ret) {
76 debug("spl_board_init_f init failed: %d\n", ret);
77 return;
78 }
79 }
80
81 #if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
board_fit_config_name_match(const char * name)82 int board_fit_config_name_match(const char *name)
83 {
84 /* boot using first FIT config */
85 return 0;
86 }
87 #endif
88