1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4 * Copyright (C) Jasbir Matharu
5 * Copyright (C) UDOO Team
6 *
7 * Author: Breno Lima <breno.lima@nxp.com>
8 * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9 */
10
11 #include <init.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/global_data.h>
18 #include <asm/gpio.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <dm.h>
21 #include <env.h>
22 #include <mmc.h>
23 #include <fsl_esdhc_imx.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/io.h>
26 #include <asm/mach-imx/mxc_i2c.h>
27 #include <asm/arch/sys_proto.h>
28 #include <spl.h>
29 #include <linux/delay.h>
30 #include <linux/sizes.h>
31 #include <common.h>
32 #include <i2c.h>
33 #include <power/pmic.h>
34 #include <power/pfuze3000_pmic.h>
35 #include <malloc.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 enum {
40 UDOO_NEO_TYPE_BASIC,
41 UDOO_NEO_TYPE_BASIC_KS,
42 UDOO_NEO_TYPE_FULL,
43 UDOO_NEO_TYPE_EXTENDED,
44 };
45
46 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
48 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53
54 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
56
57 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
59
60 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm)
62
63 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
65 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
66 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
67 MUX_MODE_SION)
68
69 #define OCRAM_START 0x8f8000
70
dram_init(void)71 int dram_init(void)
72 {
73 gd->ram_size = imx_ddr_size();
74 return 0;
75 }
76
power_init_board(void)77 int power_init_board(void)
78 {
79 struct udevice *dev;
80 int ret, dev_id, rev_id;
81
82 ret = pmic_get("pfuze3000@8", &dev);
83 if (ret == -ENODEV)
84 return 0;
85 if (ret != 0)
86 return ret;
87
88 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
89 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
90 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
91
92 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
93
94 return 0;
95 }
96
97 static iomux_v3_cfg_t const usdhc2_pads[] = {
98 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 /* CD pin */
105 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 /* Power */
107 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
108 };
109
110 static iomux_v3_cfg_t const phy_control_pads[] = {
111 /* 25MHz Ethernet PHY Clock */
112 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
113 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
114 };
115
116 static iomux_v3_cfg_t const wdog_b_pad = {
117 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
118 };
119
120 static iomux_v3_cfg_t const peri_3v3_pads[] = {
121 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
122 };
123
setup_fec(void)124 static int setup_fec(void)
125 {
126 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
127 int reg;
128
129 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
130 ARRAY_SIZE(phy_control_pads));
131
132 /* Reset PHY */
133 gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
134 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
135 udelay(10000);
136 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
137 udelay(100);
138
139 reg = readl(&anatop->pll_enet);
140 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
141 writel(reg, &anatop->pll_enet);
142
143 return enable_fec_anatop_clock(0, ENET_25MHZ);
144 }
145
board_init(void)146 int board_init(void)
147 {
148 /* Address of boot parameters */
149 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
150
151 /*
152 * Because kernel set WDOG_B mux before pad with the commone pinctrl
153 * framwork now and wdog reset will be triggered once set WDOG_B mux
154 * with default pad setting, we set pad setting here to workaround this.
155 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
156 * as GPIO mux firstly here to workaround it.
157 */
158 imx_iomux_v3_setup_pad(wdog_b_pad);
159
160 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
161 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
162 ARRAY_SIZE(peri_3v3_pads));
163
164 /* Active high for ncp692 */
165 gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
166 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
167
168 setup_fec();
169
170 return 0;
171 }
172
173 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
174 {USDHC2_BASE_ADDR},
175 };
176
177 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
178 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
179
board_mmc_getcd(struct mmc * mmc)180 int board_mmc_getcd(struct mmc *mmc)
181 {
182 return !gpio_get_value(USDHC2_CD_GPIO);
183 }
184
board_mmc_init(struct bd_info * bis)185 int board_mmc_init(struct bd_info *bis)
186 {
187 SETUP_IOMUX_PADS(usdhc2_pads);
188 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
189 usdhc_cfg[0].max_bus_width = 4;
190 gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
191 gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
192 gpio_direction_input(USDHC2_CD_GPIO);
193 gpio_direction_output(USDHC2_PWR_GPIO, 1);
194
195 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
196 }
197
board_string(int type)198 static char *board_string(int type)
199 {
200 switch (type) {
201 case UDOO_NEO_TYPE_BASIC:
202 return "BASIC";
203 case UDOO_NEO_TYPE_BASIC_KS:
204 return "BASICKS";
205 case UDOO_NEO_TYPE_FULL:
206 return "FULL";
207 case UDOO_NEO_TYPE_EXTENDED:
208 return "EXTENDED";
209 }
210 return "UNDEFINED";
211 }
212
213 /* Override the default implementation, DT model is not accurate */
show_board_info(void)214 int show_board_info(void)
215 {
216 int *board_type = (int *)OCRAM_START;
217
218 printf("Board: UDOO Neo %s\n", board_string(*board_type));
219 return 0;
220 }
221
board_late_init(void)222 int board_late_init(void)
223 {
224 int *board_type = (int *)OCRAM_START;
225
226 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
227 env_set("board_name", board_string(*board_type));
228 #endif
229
230 return 0;
231 }
232
233 #ifdef CONFIG_SPL_BUILD
234
235 #include <linux/libfdt.h>
236 #include <asm/arch/mx6-ddr.h>
237
238 static const iomux_v3_cfg_t board_recognition_pads[] = {
239 /*Connected to R184*/
240 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
241 /*Connected to R185*/
242 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
243 };
244
get_board_value(void)245 static int get_board_value(void)
246 {
247 int r184, r185;
248
249 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
250 ARRAY_SIZE(board_recognition_pads));
251
252 gpio_request(IMX_GPIO_NR(4, 13), "r184");
253 gpio_request(IMX_GPIO_NR(4, 0), "r185");
254 gpio_direction_input(IMX_GPIO_NR(4, 13));
255 gpio_direction_input(IMX_GPIO_NR(4, 0));
256
257 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
258 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
259
260 /*
261 * Machine selection -
262 * Machine r184, r185
263 * ---------------------------------
264 * Basic 0 0
265 * Basic Ks 0 1
266 * Full 1 0
267 * Extended 1 1
268 */
269
270 return (r184 << 1) + r185;
271 }
272
273 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
274 .dram_dqm0 = 0x00000028,
275 .dram_dqm1 = 0x00000028,
276 .dram_dqm2 = 0x00000028,
277 .dram_dqm3 = 0x00000028,
278 .dram_ras = 0x00000020,
279 .dram_cas = 0x00000020,
280 .dram_odt0 = 0x00000020,
281 .dram_odt1 = 0x00000020,
282 .dram_sdba2 = 0x00000000,
283 .dram_sdcke0 = 0x00003000,
284 .dram_sdcke1 = 0x00003000,
285 .dram_sdclk_0 = 0x00000030,
286 .dram_sdqs0 = 0x00000028,
287 .dram_sdqs1 = 0x00000028,
288 .dram_sdqs2 = 0x00000028,
289 .dram_sdqs3 = 0x00000028,
290 .dram_reset = 0x00000020,
291 };
292
293 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
294 .grp_addds = 0x00000020,
295 .grp_ddrmode_ctl = 0x00020000,
296 .grp_ddrpke = 0x00000000,
297 .grp_ddrmode = 0x00020000,
298 .grp_b0ds = 0x00000028,
299 .grp_b1ds = 0x00000028,
300 .grp_ctlds = 0x00000020,
301 .grp_ddr_type = 0x000c0000,
302 .grp_b2ds = 0x00000028,
303 .grp_b3ds = 0x00000028,
304 };
305
306 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
307 .p0_mpwldectrl0 = 0x000E000B,
308 .p0_mpwldectrl1 = 0x000E0010,
309 .p0_mpdgctrl0 = 0x41600158,
310 .p0_mpdgctrl1 = 0x01500140,
311 .p0_mprddlctl = 0x3A383E3E,
312 .p0_mpwrdlctl = 0x3A383C38,
313 };
314
315 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
316 .p0_mpwldectrl0 = 0x001E0022,
317 .p0_mpwldectrl1 = 0x001C0019,
318 .p0_mpdgctrl0 = 0x41540150,
319 .p0_mpdgctrl1 = 0x01440138,
320 .p0_mprddlctl = 0x403E4644,
321 .p0_mpwrdlctl = 0x3C3A4038,
322 };
323
324 /* MT41K256M16 */
325 static struct mx6_ddr3_cfg neo_mem_ddr = {
326 .mem_speed = 1600,
327 .density = 4,
328 .width = 16,
329 .banks = 8,
330 .rowaddr = 15,
331 .coladdr = 10,
332 .pagesz = 2,
333 .trcd = 1375,
334 .trcmin = 4875,
335 .trasmin = 3500,
336 };
337
338 /* MT41K128M16 */
339 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
340 .mem_speed = 1600,
341 .density = 2,
342 .width = 16,
343 .banks = 8,
344 .rowaddr = 14,
345 .coladdr = 10,
346 .pagesz = 2,
347 .trcd = 1375,
348 .trcmin = 4875,
349 .trasmin = 3500,
350 };
351
ccgr_init(void)352 static void ccgr_init(void)
353 {
354 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
355
356 writel(0xFFFFFFFF, &ccm->CCGR0);
357 writel(0xFFFFFFFF, &ccm->CCGR1);
358 writel(0xFFFFFFFF, &ccm->CCGR2);
359 writel(0xFFFFFFFF, &ccm->CCGR3);
360 writel(0xFFFFFFFF, &ccm->CCGR4);
361 writel(0xFFFFFFFF, &ccm->CCGR5);
362 writel(0xFFFFFFFF, &ccm->CCGR6);
363 writel(0xFFFFFFFF, &ccm->CCGR7);
364 }
365
spl_dram_init(void)366 static void spl_dram_init(void)
367 {
368 int *board_type = (int *)OCRAM_START;
369
370 struct mx6_ddr_sysinfo sysinfo = {
371 .dsize = 1, /* width of data bus: 1 = 32 bits */
372 .cs_density = 24,
373 .ncs = 1,
374 .cs1_mirror = 0,
375 .rtt_wr = 2,
376 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
377 .walat = 1, /* Write additional latency */
378 .ralat = 5, /* Read additional latency */
379 .mif3_mode = 3, /* Command prediction working mode */
380 .bi_on = 1, /* Bank interleaving enabled */
381 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
382 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
383 };
384
385 *board_type = get_board_value();
386
387 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
388 if (*board_type == UDOO_NEO_TYPE_BASIC ||
389 *board_type == UDOO_NEO_TYPE_BASIC_KS)
390 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
391 &neo_basic_mem_ddr);
392 else
393 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
394 }
395
board_init_f(ulong dummy)396 void board_init_f(ulong dummy)
397 {
398 ccgr_init();
399
400 /* setup AIPS and disable watchdog */
401 arch_cpu_init();
402
403 /* setup GP timer */
404 timer_init();
405
406 /* Enable device tree and early DM support*/
407 spl_early_init();
408
409 /* UART clocks enabled and gd valid - init serial console */
410 preloader_console_init();
411
412 /* DDR initialization */
413 spl_dram_init();
414
415 /* Clear the BSS. */
416 memset(__bss_start, 0, __bss_end - __bss_start);
417
418 /* load/boot image from boot device */
419 board_init_r(NULL, 0);
420 }
421
422 #endif
423