1if TARGET_MICROBLAZE_GENERIC
2
3config SYS_BOARD
4	default "microblaze-generic"
5
6config SYS_VENDOR
7	default "xilinx"
8
9config SYS_CONFIG_NAME
10	string "Board configuration name"
11	default "microblaze-generic"
12	help
13	  This option contains information about board configuration name.
14	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
15	  will be used for board configuration.
16
17config XILINX_MICROBLAZE0_USE_MSR_INSTR
18	int "USE_MSR_INSTR range (0:1)"
19	default 0
20
21config XILINX_MICROBLAZE0_USE_PCMP_INSTR
22	int "USE_PCMP_INSTR range (0:1)"
23	default 0
24
25config XILINX_MICROBLAZE0_USE_BARREL
26	int "USE_BARREL range (0:1)"
27	default 0
28
29config XILINX_MICROBLAZE0_USE_DIV
30	int "USE_DIV range (0:1)"
31	default 0
32
33config XILINX_MICROBLAZE0_USE_HW_MUL
34	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
35	default 0
36
37config XILINX_MICROBLAZE0_HW_VER
38	string "Core version number"
39	default "7.10.d"
40
41config XILINX_MICROBLAZE0_FPGA_FAMILY
42	string "Targeted FPGA family"
43	default "virtex5"
44	help
45	  This option contains info about the target FPGA architecture
46	  (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is
47	  implemented on. It corresponds to the C_FAMILY hdl parameter.
48
49config XILINX_MICROBLAZE0_USR_EXCEP
50	bool "MicroBlaze user exception support"
51	default y
52	help
53	  Enable this option in order to install the user exception handler
54	  (_exception_handler routine from arch/microblaze/cpu/exception.c) in
55	  the exception vector table. The user exception vector is located at
56	  C_BASE_VECTORS + 0x8 address.
57
58config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
59	bool "MicroBlaze delay slot exception support"
60	default y
61	help
62	  Enable this option if the MicroBlaze processor supports exceptions
63	  caused by delay slot instructions (processor version >= v5.00). When
64	  enabled, the hw exception handler will print a message indicating
65	  whether the exception was triggered by a delay slot instruction.
66
67config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
68	hex "Location of MicroBlaze vectors"
69	default 0x0
70	help
71	  Memory address location of the exception vector table. It is
72	  configurable via the C_BASE_VECTORS hdl parameter.
73
74config XILINX_MICROBLAZE0_USE_WDC
75	bool "MicroBlaze wdc instruction support"
76	default y
77	help
78	  Enable this option if the MicroBlaze processor is configured with
79	  support for the "wdc" (Write to Data Cache) instruction.
80
81config SPL_XILINX_MICROBLAZE0_USE_WDC
82	bool
83	default XILINX_MICROBLAZE0_USE_WDC
84
85config XILINX_MICROBLAZE0_USE_WIC
86	bool "MicroBlaze wic instruction support"
87	default y
88	help
89	  Enable this option if the MicroBlaze processor is configured with
90	  support for the "wic" (Write to Instruction Cache) instruction.
91
92config SPL_XILINX_MICROBLAZE0_USE_WIC
93	bool
94	default XILINX_MICROBLAZE0_USE_WIC
95
96config XILINX_MICROBLAZE0_DCACHE_SIZE
97	int "Default data cache size"
98	default 32768
99	help
100	  This fallback size will be used when no dcache info can be found in
101	  the device tree, or when the data cache is flushed very early in the
102	  boot process, before device tree is available.
103
104config XILINX_MICROBLAZE0_ICACHE_SIZE
105	int "Default instruction cache size"
106	default 32768
107	help
108	  This fallback size will be used when no icache info can be found in
109	  the device tree, or when the instruction cache is flushed very early
110	  in the boot process, before device tree is available.
111
112config XILINX_MICROBLAZE0_PVR
113	bool "MicroBlaze PVR support"
114	help
115	  Enables helper functions and macros needed to manipulate PVR
116	  (Processor Version Register) data. Currently, only the microblaze
117	  UCLASS_CPU driver makes use of this feature to retrieve CPU info at
118	  runtime.
119
120endif
121