1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7 #include <command.h>
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <env.h>
11 #include <fdtdec.h>
12 #include <init.h>
13 #include <env_internal.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <time.h>
17 #include <asm/cache.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/sys_proto.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
24 #include <versalpl.h>
25 #include "../common/board.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 #if defined(CONFIG_FPGA_VERSALPL)
30 static xilinx_desc versalpl = {
31 xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
32 FPGA_LEGACY
33 };
34 #endif
35
board_init(void)36 int board_init(void)
37 {
38 printf("EL Level:\tEL%d\n", current_el());
39
40 #if defined(CONFIG_FPGA_VERSALPL)
41 fpga_init();
42 fpga_add(fpga_xilinx, &versalpl);
43 #endif
44
45 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
46 xilinx_read_eeprom();
47
48 return 0;
49 }
50
board_early_init_r(void)51 int board_early_init_r(void)
52 {
53 u32 val;
54
55 if (current_el() != 3)
56 return 0;
57
58 debug("iou_switch ctrl div0 %x\n",
59 readl(&crlapb_base->iou_switch_ctrl));
60
61 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
62 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
63 &crlapb_base->iou_switch_ctrl);
64
65 /* Global timer init - Program time stamp reference clk */
66 val = readl(&crlapb_base->timestamp_ref_ctrl);
67 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
68 writel(val, &crlapb_base->timestamp_ref_ctrl);
69
70 debug("ref ctrl 0x%x\n",
71 readl(&crlapb_base->timestamp_ref_ctrl));
72
73 /* Clear reset of timestamp reg */
74 writel(0, &crlapb_base->rst_timestamp);
75
76 /*
77 * Program freq register in System counter and
78 * enable system counter.
79 */
80 writel(CONFIG_COUNTER_FREQUENCY,
81 &iou_scntr_secure->base_frequency_id_register);
82
83 debug("counter val 0x%x\n",
84 readl(&iou_scntr_secure->base_frequency_id_register));
85
86 writel(IOU_SCNTRS_CONTROL_EN,
87 &iou_scntr_secure->counter_control_register);
88
89 debug("scntrs control 0x%x\n",
90 readl(&iou_scntr_secure->counter_control_register));
91 debug("timer 0x%llx\n", get_ticks());
92 debug("timer 0x%llx\n", get_ticks());
93
94 return 0;
95 }
96
do_go_exec(ulong (* entry)(int,char * const[]),int argc,char * const argv[])97 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
98 char *const argv[])
99 {
100 int ret = 0;
101
102 if (current_el() > 1) {
103 smp_kick_all_cpus();
104 dcache_disable();
105 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
106 ES_TO_AARCH64);
107 } else {
108 printf("FAIL: current EL is not above EL1\n");
109 ret = EINVAL;
110 }
111 return ret;
112 }
113
versal_get_bootmode(void)114 static u8 versal_get_bootmode(void)
115 {
116 u8 bootmode;
117 u32 reg = 0;
118
119 reg = readl(&crp_base->boot_mode_usr);
120
121 if (reg >> BOOT_MODE_ALT_SHIFT)
122 reg >>= BOOT_MODE_ALT_SHIFT;
123
124 bootmode = reg & BOOT_MODES_MASK;
125
126 return bootmode;
127 }
128
board_late_init(void)129 int board_late_init(void)
130 {
131 u8 bootmode;
132 struct udevice *dev;
133 int bootseq = -1;
134 int bootseq_len = 0;
135 int env_targets_len = 0;
136 const char *mode;
137 char *new_targets;
138 char *env_targets;
139
140 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
141 debug("Saved variables - Skipping\n");
142 return 0;
143 }
144
145 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
146 return 0;
147
148 bootmode = versal_get_bootmode();
149
150 puts("Bootmode: ");
151 switch (bootmode) {
152 case USB_MODE:
153 puts("USB_MODE\n");
154 mode = "usb_dfu0 usb_dfu1";
155 break;
156 case JTAG_MODE:
157 puts("JTAG_MODE\n");
158 mode = "jtag pxe dhcp";
159 break;
160 case QSPI_MODE_24BIT:
161 puts("QSPI_MODE_24\n");
162 mode = "xspi0";
163 break;
164 case QSPI_MODE_32BIT:
165 puts("QSPI_MODE_32\n");
166 mode = "xspi0";
167 break;
168 case OSPI_MODE:
169 puts("OSPI_MODE\n");
170 mode = "xspi0";
171 break;
172 case EMMC_MODE:
173 puts("EMMC_MODE\n");
174 if (uclass_get_device_by_name(UCLASS_MMC,
175 "mmc@f1050000", &dev) &&
176 uclass_get_device_by_name(UCLASS_MMC,
177 "sdhci@f1050000", &dev)) {
178 puts("Boot from EMMC but without SD1 enabled!\n");
179 return -1;
180 }
181 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
182 mode = "mmc";
183 bootseq = dev_seq(dev);
184 break;
185 case SD_MODE:
186 puts("SD_MODE\n");
187 if (uclass_get_device_by_name(UCLASS_MMC,
188 "mmc@f1040000", &dev) &&
189 uclass_get_device_by_name(UCLASS_MMC,
190 "sdhci@f1040000", &dev)) {
191 puts("Boot from SD0 but without SD0 enabled!\n");
192 return -1;
193 }
194 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
195
196 mode = "mmc";
197 bootseq = dev_seq(dev);
198 break;
199 case SD1_LSHFT_MODE:
200 puts("LVL_SHFT_");
201 /* fall through */
202 case SD_MODE1:
203 puts("SD_MODE1\n");
204 if (uclass_get_device_by_name(UCLASS_MMC,
205 "mmc@f1050000", &dev) &&
206 uclass_get_device_by_name(UCLASS_MMC,
207 "sdhci@f1050000", &dev)) {
208 puts("Boot from SD1 but without SD1 enabled!\n");
209 return -1;
210 }
211 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
212
213 mode = "mmc";
214 bootseq = dev_seq(dev);
215 break;
216 default:
217 mode = "";
218 printf("Invalid Boot Mode:0x%x\n", bootmode);
219 break;
220 }
221
222 if (bootseq >= 0) {
223 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
224 debug("Bootseq len: %x\n", bootseq_len);
225 }
226
227 /*
228 * One terminating char + one byte for space between mode
229 * and default boot_targets
230 */
231 env_targets = env_get("boot_targets");
232 if (env_targets)
233 env_targets_len = strlen(env_targets);
234
235 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
236 bootseq_len);
237 if (!new_targets)
238 return -ENOMEM;
239
240 if (bootseq >= 0)
241 sprintf(new_targets, "%s%x %s", mode, bootseq,
242 env_targets ? env_targets : "");
243 else
244 sprintf(new_targets, "%s %s", mode,
245 env_targets ? env_targets : "");
246
247 env_set("boot_targets", new_targets);
248
249 return board_late_init_xilinx();
250 }
251
dram_init_banksize(void)252 int dram_init_banksize(void)
253 {
254 int ret;
255
256 ret = fdtdec_setup_memory_banksize();
257 if (ret)
258 return ret;
259
260 mem_map_fill();
261
262 return 0;
263 }
264
dram_init(void)265 int dram_init(void)
266 {
267 if (fdtdec_setup_mem_size_base_lowest() != 0)
268 return -EINVAL;
269
270 return 0;
271 }
272
reset_cpu(void)273 void reset_cpu(void)
274 {
275 }
276
env_get_location(enum env_operation op,int prio)277 enum env_location env_get_location(enum env_operation op, int prio)
278 {
279 u32 bootmode = versal_get_bootmode();
280
281 if (prio)
282 return ENVL_UNKNOWN;
283
284 switch (bootmode) {
285 case EMMC_MODE:
286 case SD_MODE:
287 case SD1_LSHFT_MODE:
288 case SD_MODE1:
289 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
290 return ENVL_FAT;
291 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
292 return ENVL_EXT4;
293 return ENVL_NOWHERE;
294 case OSPI_MODE:
295 case QSPI_MODE_24BIT:
296 case QSPI_MODE_32BIT:
297 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
298 return ENVL_SPI_FLASH;
299 return ENVL_NOWHERE;
300 case JTAG_MODE:
301 default:
302 return ENVL_NOWHERE;
303 }
304 }
305