1#
2# Cache controllers
3#
4
5menu "Cache Controller drivers"
6
7config CACHE
8	bool "Enable Driver Model for Cache controllers"
9	depends on DM
10	help
11	  Enable driver model for cache controllers that are found on
12	  most CPU's. Cache is memory that the CPU can access directly and
13	  is usually located on the same chip. This uclass can be used for
14	  configuring settings that be found from a device tree file.
15
16config L2X0_CACHE
17	tristate "PL310 cache driver"
18	select CACHE
19	depends on ARM
20	help
21	  This driver is for the PL310 cache controller commonly found on
22	  ARMv7(32-bit) devices. The driver configures the cache settings
23	  found in the device tree.
24
25config V5L2_CACHE
26	bool "Andes V5L2 cache driver"
27	select CACHE
28	help
29	  Support Andes V5L2 cache controller in AE350 platform.
30	  It will configure tag and data ram timing control from the
31	  device tree and enable L2 cache.
32
33config NCORE_CACHE
34	bool "Arteris Ncore cache coherent unit driver"
35	select CACHE
36	help
37	  This driver is for the Arteris Ncore cache coherent unit (CCU)
38	  controller. The driver initializes cache directories and coherent
39	  agent interfaces.
40
41config SIFIVE_CCACHE
42	bool "SiFive composable cache"
43	select CACHE
44	help
45	  This driver is for SiFive Composable L2/L3 cache. It enables cache
46	  ways of composable cache.
47
48endmenu
49