1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <cache.h>
10 #include <dm.h>
11 #include <hang.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <dm/ofnode.h>
15 #include <linux/bitops.h>
16
17 struct l2cache {
18 volatile u64 configure;
19 volatile u64 control;
20 volatile u64 hpm0;
21 volatile u64 hpm1;
22 volatile u64 hpm2;
23 volatile u64 hpm3;
24 volatile u64 error_status;
25 volatile u64 ecc_error;
26 volatile u64 cctl_command0;
27 volatile u64 cctl_access_line0;
28 volatile u64 cctl_command1;
29 volatile u64 cctl_access_line1;
30 volatile u64 cctl_command2;
31 volatile u64 cctl_access_line2;
32 volatile u64 cctl_command3;
33 volatile u64 cctl_access_line4;
34 volatile u64 cctl_status;
35 };
36
37 /* Configuration register */
38 #define MEM_MAP_OFF 20
39 #define MEM_MAP_MSK BIT(MEM_MAP_OFF)
40 /* offset of v0 memory map (Gen1) */
41 static u32 cmd_stride = 0x10;
42 static u32 status_stride = 0x0;
43 static u32 status_bit_offset = 0x4;
44
45 /* Control Register */
46 #define L2_ENABLE 0x1
47 /* prefetch */
48 #define IPREPETCH_OFF 3
49 #define DPREPETCH_OFF 5
50 #define IPREPETCH_MSK (3 << IPREPETCH_OFF)
51 #define DPREPETCH_MSK (3 << DPREPETCH_OFF)
52 /* tag ram */
53 #define TRAMOCTL_OFF 8
54 #define TRAMICTL_OFF 10
55 #define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
56 #define TRAMICTL_MSK BIT(TRAMICTL_OFF)
57 /* data ram */
58 #define DRAMOCTL_OFF 11
59 #define DRAMICTL_OFF 13
60 #define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
61 #define DRAMICTL_MSK BIT(DRAMICTL_OFF)
62
63 /* CCTL Command Register */
64 #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride))
65 #define L2_WBINVAL_ALL 0x12
66
67 /* CCTL Status Register */
68 #define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride))
69 #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset)))
70 #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset)))
71 #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset)))
72 #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset)))
73
74 DECLARE_GLOBAL_DATA_PTR;
75
76 struct v5l2_plat {
77 struct l2cache *regs;
78 u32 iprefetch;
79 u32 dprefetch;
80 u32 tram_ctl[2];
81 u32 dram_ctl[2];
82 };
83
v5l2_enable(struct udevice * dev)84 static int v5l2_enable(struct udevice *dev)
85 {
86 struct v5l2_plat *plat = dev_get_plat(dev);
87 volatile struct l2cache *regs = plat->regs;
88
89 if (regs)
90 setbits_le32(®s->control, L2_ENABLE);
91
92 return 0;
93 }
94
v5l2_disable(struct udevice * dev)95 static int v5l2_disable(struct udevice *dev)
96 {
97 struct v5l2_plat *plat = dev_get_plat(dev);
98 volatile struct l2cache *regs = plat->regs;
99 u8 hart = gd->arch.boot_hart;
100 void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
101
102 if ((regs) && (readl(®s->control) & L2_ENABLE)) {
103 writel(L2_WBINVAL_ALL, cctlcmd);
104
105 while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
106 if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
107 printf("L2 flush illegal! hanging...");
108 hang();
109 }
110 }
111 clrbits_le32(®s->control, L2_ENABLE);
112 }
113
114 return 0;
115 }
116
v5l2_of_to_plat(struct udevice * dev)117 static int v5l2_of_to_plat(struct udevice *dev)
118 {
119 struct v5l2_plat *plat = dev_get_plat(dev);
120 struct l2cache *regs;
121
122 regs = dev_read_addr_ptr(dev);
123 plat->regs = regs;
124
125 plat->iprefetch = -EINVAL;
126 plat->dprefetch = -EINVAL;
127 plat->tram_ctl[0] = -EINVAL;
128 plat->dram_ctl[0] = -EINVAL;
129
130 /* Instruction and data fetch prefetch depth */
131 dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
132 dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
133
134 /* Set tag RAM and data RAM setup and output cycle */
135 dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
136 dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
137
138 return 0;
139 }
140
v5l2_probe(struct udevice * dev)141 static int v5l2_probe(struct udevice *dev)
142 {
143 struct v5l2_plat *plat = dev_get_plat(dev);
144 struct l2cache *regs = plat->regs;
145 u32 cfg_val, ctl_val;
146
147 cfg_val = readl(®s->configure);
148 ctl_val = readl(®s->control);
149
150 /* If true, v1 memory map (Gen2) */
151 if (cfg_val & MEM_MAP_MSK) {
152 cmd_stride = 0x1000;
153 status_stride = 0x1000;
154 status_bit_offset = 0x0;
155 }
156
157 ctl_val |= L2_ENABLE;
158
159 if (plat->iprefetch != -EINVAL) {
160 ctl_val &= ~(IPREPETCH_MSK);
161 ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
162 }
163
164 if (plat->dprefetch != -EINVAL) {
165 ctl_val &= ~(DPREPETCH_MSK);
166 ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
167 }
168
169 if (plat->tram_ctl[0] != -EINVAL) {
170 ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
171 ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
172 ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
173 }
174
175 if (plat->dram_ctl[0] != -EINVAL) {
176 ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
177 ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
178 ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
179 }
180
181 writel(ctl_val, ®s->control);
182
183 return 0;
184 }
185
186 static const struct udevice_id v5l2_cache_ids[] = {
187 { .compatible = "cache" },
188 {}
189 };
190
191 static const struct cache_ops v5l2_cache_ops = {
192 .enable = v5l2_enable,
193 .disable = v5l2_disable,
194 };
195
196 U_BOOT_DRIVER(v5l2_cache) = {
197 .name = "v5l2_cache",
198 .id = UCLASS_CACHE,
199 .of_match = v5l2_cache_ids,
200 .of_to_plat = v5l2_of_to_plat,
201 .probe = v5l2_probe,
202 .plat_auto = sizeof(struct v5l2_plat),
203 .ops = &v5l2_cache_ops,
204 .flags = DM_FLAG_PRE_RELOC,
205 };
206