1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
4 */
5
6 #include <common.h>
7 #include <asm/arch/clock_manager.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include "clk-mem-n5x.h"
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <dm/lists.h>
14 #include <dm/util.h>
15 #include <dt-bindings/clock/n5x-clock.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 struct socfpga_mem_clk_plat {
20 void __iomem *regs;
21 };
22
clk_mem_wait_for_lock(struct socfpga_mem_clk_plat * plat,u32 mask)23 void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
24 {
25 u32 inter_val;
26 u32 retry = 0;
27
28 do {
29 inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
30
31 /* Wait for stable lock */
32 if (inter_val == mask)
33 retry++;
34 else
35 retry = 0;
36
37 if (retry >= 10)
38 return;
39 } while (1);
40 }
41
42 /*
43 * function to write the bypass register which requires a poll of the
44 * busy bit
45 */
clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat * plat,u32 val)46 void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
47 {
48 CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
49 }
50
51 /*
52 * Setup clocks while making no assumptions about previous state of the clocks.
53 */
clk_mem_basic_init(struct udevice * dev,const struct cm_config * const cfg)54 static void clk_mem_basic_init(struct udevice *dev,
55 const struct cm_config * const cfg)
56 {
57 struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
58
59 if (!cfg)
60 return;
61
62 /* Put PLLs in bypass */
63 clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
64
65 /* Put PLLs in Reset */
66 CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
67 MEMCLKMGR_PLLCTRL_BYPASS_MASK);
68
69 /* setup mem PLL */
70 CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
71 CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
72 CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
73 CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
74
75 /* Take PLL out of reset and power up */
76 CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
77 MEMCLKMGR_PLLCTRL_BYPASS_MASK);
78 }
79
socfpga_mem_clk_enable(struct clk * clk)80 static int socfpga_mem_clk_enable(struct clk *clk)
81 {
82 const struct cm_config *cm_default_cfg = cm_get_default_config();
83 struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
84
85 clk_mem_basic_init(clk->dev, cm_default_cfg);
86
87 clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
88
89 CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
90 MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
91 MEMCLKMGR_MEMPLL_PLLGLOB);
92
93 /* Take all PLLs out of bypass */
94 clk_mem_write_bypass_mempll(plat, 0);
95
96 /* Clear the loss of lock bits (write 1 to clear) */
97 CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
98 MEMCLKMGR_INTER_MEMPLLLOST_MASK);
99
100 /* Take all ping pong counters out of reset */
101 CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
102 MEMCLKMGR_EXTCNTRST_ALLCNTRST);
103
104 return 0;
105 }
106
socfpga_mem_clk_of_to_plat(struct udevice * dev)107 static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
108 {
109 struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
110 fdt_addr_t addr;
111
112 addr = devfdt_get_addr(dev);
113 if (addr == FDT_ADDR_T_NONE)
114 return -EINVAL;
115 plat->regs = (void __iomem *)addr;
116
117 return 0;
118 }
119
120 static struct clk_ops socfpga_mem_clk_ops = {
121 .enable = socfpga_mem_clk_enable
122 };
123
124 static const struct udevice_id socfpga_mem_clk_match[] = {
125 { .compatible = "intel,n5x-mem-clkmgr" },
126 {}
127 };
128
129 U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
130 .name = "mem-clk-n5x",
131 .id = UCLASS_CLK,
132 .of_match = socfpga_mem_clk_match,
133 .ops = &socfpga_mem_clk_ops,
134 .of_to_plat = socfpga_mem_clk_of_to_plat,
135 .plat_auto = sizeof(struct socfpga_mem_clk_plat),
136 };
137