1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
4  */
5 
6 #ifndef	_CLK_MEM_N5X_
7 #define	_CLK_MEM_N5X_
8 
9 #ifndef __ASSEMBLY__
10 #include <linux/bitops.h>
11 #endif
12 
13 /* Clock Manager registers */
14 #define MEMCLKMGR_STAT					4
15 #define MEMCLKMGR_INTRGEN				8
16 #define MEMCLKMGR_INTRMSK				0x0c
17 #define MEMCLKMGR_INTRCLR				0x10
18 #define MEMCLKMGR_INTRSTS				0x14
19 #define MEMCLKMGR_INTRSTK				0x18
20 #define MEMCLKMGR_INTRRAW				0x1c
21 
22 /* Memory Clock Manager PPL group registers */
23 #define MEMCLKMGR_MEMPLL_EN				0x20
24 #define MEMCLKMGR_MEMPLL_ENS				0x24
25 #define MEMCLKMGR_MEMPLL_ENR				0x28
26 #define MEMCLKMGR_MEMPLL_BYPASS				0x2c
27 #define MEMCLKMGR_MEMPLL_BYPASSS			0x30
28 #define MEMCLKMGR_MEMPLL_BYPASSR			0x34
29 #define MEMCLKMGR_MEMPLL_MEMDIV				0x38
30 #define MEMCLKMGR_MEMPLL_PLLGLOB			0x3c
31 #define MEMCLKMGR_MEMPLL_PLLCTRL			0x40
32 #define MEMCLKMGR_MEMPLL_PLLDIV				0x44
33 #define MEMCLKMGR_MEMPLL_PLLOUTDIV			0x48
34 #define MEMCLKMGR_MEMPLL_EXTCNTRST			0x4c
35 
36 #define MEMCLKMGR_CTRL_BOOTMODE				BIT(0)
37 
38 #define MEMCLKMGR_STAT_MEMPLL_LOCKED			BIT(8)
39 
40 #define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK		\
41 	(MEMCLKMGR_STAT_MEMPLL_LOCKED)
42 
43 #define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK		BIT(0)
44 #define MEMCLKMGR_INTER_MEMPLLLOST_MASK			BIT(2)
45 
46 #define MEMCLKMGR_BYPASS_MEMPLL_ALL			0x1
47 
48 #define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET			0
49 #define MEMCLKMGR_MEMDIV_APBDIV_OFFSET			4
50 #define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET		8
51 #define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET			12
52 #define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK		BIT(0)
53 #define MEMCLKMGR_MEMDIV_DIVIDER_MASK			GENMASK(1, 0)
54 
55 #define MEMCLKMGR_PLLGLOB_PSRC_MASK			GENMASK(17, 16)
56 #define MEMCLKMGR_PLLGLOB_PSRC_OFFSET			16
57 #define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK	BIT(28)
58 #define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK	BIT(29)
59 
60 #define MEMCLKMGR_PSRC_EOSC1				0
61 #define MEMCLKMGR_PSRC_INTOSC				1
62 #define MEMCLKMGR_PSRC_F2S				2
63 
64 #define MEMCLKMGR_PLLCTRL_BYPASS_MASK			BIT(0)
65 #define MEMCLKMGR_PLLCTRL_RST_N_MASK			BIT(1)
66 
67 #define MEMCLKMGR_PLLDIV_DIVR_MASK			GENMASK(5, 0)
68 #define MEMCLKMGR_PLLDIV_DIVF_MASK			GENMASK(16, 8)
69 #define MEMCLKMGR_PLLDIV_DIVQ_MASK			GENMASK(26, 24)
70 #define MEMCLKMGR_PLLDIV_RANGE_MASK			GENMASK(30, 28)
71 
72 #define MEMCLKMGR_PLLDIV_DIVR_OFFSET			0
73 #define MEMCLKMGR_PLLDIV_DIVF_OFFSET			8
74 #define MEMCLKMGR_PLLDIV_DIVQ_QDIV_OFFSET		24
75 #define MEMCLKMGR_PLLDIV_RANGE_OFFSET			28
76 
77 #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK			GENMASK(4, 0)
78 #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET		0
79 
80 #define MEMCLKMGR_EXTCNTRST_C0CNTRST			BIT(7)
81 #define MEMCLKMGR_EXTCNTRST_ALLCNTRST			\
82 	(MEMCLKMGR_EXTCNTRST_C0CNTRST)
83 
84 #endif /* _CLK_MEM_N5X_ */
85