1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Author: Anup Patel <anup.patel@wdc.com>
6 */
7
8 #define LOG_CATEGORY UCLASS_CLK
9
10 #include <common.h>
11 #include <clk-uclass.h>
12 #include <div64.h>
13 #include <dm.h>
14 #include <log.h>
15 #include <linux/err.h>
16
17 struct clk_fixed_factor {
18 struct clk parent;
19 unsigned int div;
20 unsigned int mult;
21 };
22
23 #define to_clk_fixed_factor(dev) \
24 ((struct clk_fixed_factor *)dev_get_plat(dev))
25
clk_fixed_factor_get_rate(struct clk * clk)26 static ulong clk_fixed_factor_get_rate(struct clk *clk)
27 {
28 uint64_t rate;
29 struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
30
31 rate = clk_get_rate(&ff->parent);
32 if (IS_ERR_VALUE(rate))
33 return rate;
34
35 do_div(rate, ff->div);
36
37 return rate * ff->mult;
38 }
39
40 const struct clk_ops clk_fixed_factor_ops = {
41 .get_rate = clk_fixed_factor_get_rate,
42 };
43
clk_fixed_factor_of_to_plat(struct udevice * dev)44 static int clk_fixed_factor_of_to_plat(struct udevice *dev)
45 {
46 if (CONFIG_IS_ENABLED(OF_REAL)) {
47 int err;
48 struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
49
50 err = clk_get_by_index(dev, 0, &ff->parent);
51 if (err)
52 return err;
53
54 ff->div = dev_read_u32_default(dev, "clock-div", 1);
55 ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
56 }
57
58 return 0;
59 }
60
61 static const struct udevice_id clk_fixed_factor_match[] = {
62 {
63 .compatible = "fixed-factor-clock",
64 },
65 { /* sentinel */ }
66 };
67
68 U_BOOT_DRIVER(clk_fixed_factor) = {
69 .name = "fixed_factor_clock",
70 .id = UCLASS_CLK,
71 .of_match = clk_fixed_factor_match,
72 .of_to_plat = clk_fixed_factor_of_to_plat,
73 .plat_auto = sizeof(struct clk_fixed_factor),
74 .ops = &clk_fixed_factor_ops,
75 };
76