1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <dt-bindings/clock/imx8mn-clock.h>
15
16 #include "clk.h"
17
18 static u32 share_count_nand;
19
20 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
21 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
22 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
23 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
24 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
25 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
26
27 static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
28 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
29
30 static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
31 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
32
33 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
34 "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
35
36 #ifndef CONFIG_SPL_BUILD
37 static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
38 "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };
39
40 static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
41 "clk_ext3", "clk_ext4", "video_pll_out", };
42
43 static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
44 "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
45 #endif
46
47 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
48 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
49
50 static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
51 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
52 "clk_ext4", "audio_pll2_out", };
53
54 static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
55 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
56
57 static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
58 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
59
60 #if CONFIG_IS_ENABLED(DM_SPI)
61 static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
62 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
63 "sys_pll2_250m", "audio_pll2_out", };
64
65 static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
66 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
67 "sys_pll2_250m", "audio_pll2_out", };
68
69 static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
70 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
71 "sys_pll2_250m", "audio_pll2_out", };
72 #endif
73
74 static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
75 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
76
77 static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
78 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
79
80 static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
81 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
82
83 static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
84 "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
85
86 static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll",
87 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
88
89 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
90 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
91
92 static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
93 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
94
95 static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
96 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
97 "sys_pll2_250m", "video_pll_out", };
98
99 static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
100 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
101 "clk_ext3", "audio_pll2_out", };
102
103 static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
104 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
105 "clk_ext3", "audio_pll2_out", };
106
imx8mn_clk_probe(struct udevice * dev)107 static int imx8mn_clk_probe(struct udevice *dev)
108 {
109 void __iomem *base;
110
111 base = (void *)ANATOP_BASE_ADDR;
112
113 clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
114 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
115 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
116 clk_dm(IMX8MN_ARM_PLL_REF_SEL,
117 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
118 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
119 clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
120 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
121 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
122 clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
123 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
124 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
125 clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
126 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
127 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
128
129 clk_dm(IMX8MN_DRAM_PLL,
130 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
131 base + 0x50, &imx_1443x_dram_pll));
132 clk_dm(IMX8MN_ARM_PLL,
133 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
134 base + 0x84, &imx_1416x_pll));
135 clk_dm(IMX8MN_SYS_PLL1,
136 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
137 base + 0x94, &imx_1416x_pll));
138 clk_dm(IMX8MN_SYS_PLL2,
139 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
140 base + 0x104, &imx_1416x_pll));
141 clk_dm(IMX8MN_SYS_PLL3,
142 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
143 base + 0x114, &imx_1416x_pll));
144
145 /* PLL bypass out */
146 clk_dm(IMX8MN_DRAM_PLL_BYPASS,
147 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
148 dram_pll_bypass_sels,
149 ARRAY_SIZE(dram_pll_bypass_sels),
150 CLK_SET_RATE_PARENT));
151 clk_dm(IMX8MN_ARM_PLL_BYPASS,
152 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
153 arm_pll_bypass_sels,
154 ARRAY_SIZE(arm_pll_bypass_sels),
155 CLK_SET_RATE_PARENT));
156 clk_dm(IMX8MN_SYS_PLL1_BYPASS,
157 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
158 sys_pll1_bypass_sels,
159 ARRAY_SIZE(sys_pll1_bypass_sels),
160 CLK_SET_RATE_PARENT));
161 clk_dm(IMX8MN_SYS_PLL2_BYPASS,
162 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
163 sys_pll2_bypass_sels,
164 ARRAY_SIZE(sys_pll2_bypass_sels),
165 CLK_SET_RATE_PARENT));
166 clk_dm(IMX8MN_SYS_PLL3_BYPASS,
167 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
168 sys_pll3_bypass_sels,
169 ARRAY_SIZE(sys_pll3_bypass_sels),
170 CLK_SET_RATE_PARENT));
171
172 /* PLL out gate */
173 clk_dm(IMX8MN_DRAM_PLL_OUT,
174 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
175 base + 0x50, 13));
176 clk_dm(IMX8MN_ARM_PLL_OUT,
177 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
178 base + 0x84, 11));
179 clk_dm(IMX8MN_SYS_PLL1_OUT,
180 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
181 base + 0x94, 11));
182 clk_dm(IMX8MN_SYS_PLL2_OUT,
183 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
184 base + 0x104, 11));
185 clk_dm(IMX8MN_SYS_PLL3_OUT,
186 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
187 base + 0x114, 11));
188
189 /* SYS PLL fixed output */
190 clk_dm(IMX8MN_SYS_PLL1_40M,
191 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
192 clk_dm(IMX8MN_SYS_PLL1_80M,
193 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
194 clk_dm(IMX8MN_SYS_PLL1_100M,
195 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
196 clk_dm(IMX8MN_SYS_PLL1_133M,
197 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
198 clk_dm(IMX8MN_SYS_PLL1_160M,
199 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
200 clk_dm(IMX8MN_SYS_PLL1_200M,
201 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
202 clk_dm(IMX8MN_SYS_PLL1_266M,
203 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
204 clk_dm(IMX8MN_SYS_PLL1_400M,
205 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
206 clk_dm(IMX8MN_SYS_PLL1_800M,
207 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
208
209 clk_dm(IMX8MN_SYS_PLL2_50M,
210 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
211 clk_dm(IMX8MN_SYS_PLL2_100M,
212 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
213 clk_dm(IMX8MN_SYS_PLL2_125M,
214 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
215 clk_dm(IMX8MN_SYS_PLL2_166M,
216 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
217 clk_dm(IMX8MN_SYS_PLL2_200M,
218 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
219 clk_dm(IMX8MN_SYS_PLL2_250M,
220 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
221 clk_dm(IMX8MN_SYS_PLL2_333M,
222 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
223 clk_dm(IMX8MN_SYS_PLL2_500M,
224 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
225 clk_dm(IMX8MN_SYS_PLL2_1000M,
226 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
227
228 base = dev_read_addr_ptr(dev);
229 if (!base)
230 return -EINVAL;
231
232 clk_dm(IMX8MN_CLK_A53_SRC,
233 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
234 imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
235 clk_dm(IMX8MN_CLK_A53_CG,
236 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
237 clk_dm(IMX8MN_CLK_A53_DIV,
238 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
239 base + 0x8000, 0, 3));
240
241 clk_dm(IMX8MN_CLK_AHB,
242 imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
243 base + 0x9000));
244 clk_dm(IMX8MN_CLK_IPG_ROOT,
245 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
246
247 clk_dm(IMX8MN_CLK_ENET_AXI,
248 imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
249 base + 0x8880));
250 clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
251 imx8m_clk_composite_critical("nand_usdhc_bus",
252 imx8mn_nand_usdhc_sels,
253 base + 0x8900));
254 clk_dm(IMX8MN_CLK_USB_BUS,
255 imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
256
257 /* IP */
258 clk_dm(IMX8MN_CLK_USDHC1,
259 imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
260 base + 0xac00));
261 clk_dm(IMX8MN_CLK_USDHC2,
262 imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
263 base + 0xac80));
264 clk_dm(IMX8MN_CLK_I2C1,
265 imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
266 clk_dm(IMX8MN_CLK_I2C2,
267 imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
268 clk_dm(IMX8MN_CLK_I2C3,
269 imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
270 clk_dm(IMX8MN_CLK_I2C4,
271 imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
272 clk_dm(IMX8MN_CLK_WDOG,
273 imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
274 clk_dm(IMX8MN_CLK_USDHC3,
275 imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
276 base + 0xbc80));
277 clk_dm(IMX8MN_CLK_NAND,
278 imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
279 clk_dm(IMX8MN_CLK_QSPI,
280 imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
281 clk_dm(IMX8MN_CLK_USB_CORE_REF,
282 imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
283 clk_dm(IMX8MN_CLK_USB_PHY_REF,
284 imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
285
286 clk_dm(IMX8MN_CLK_I2C1_ROOT,
287 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
288 clk_dm(IMX8MN_CLK_I2C2_ROOT,
289 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
290 clk_dm(IMX8MN_CLK_I2C3_ROOT,
291 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
292 clk_dm(IMX8MN_CLK_I2C4_ROOT,
293 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
294 clk_dm(IMX8MN_CLK_OCOTP_ROOT,
295 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
296 clk_dm(IMX8MN_CLK_USDHC1_ROOT,
297 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
298 clk_dm(IMX8MN_CLK_USDHC2_ROOT,
299 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
300 clk_dm(IMX8MN_CLK_WDOG1_ROOT,
301 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
302 clk_dm(IMX8MN_CLK_WDOG2_ROOT,
303 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
304 clk_dm(IMX8MN_CLK_WDOG3_ROOT,
305 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
306 clk_dm(IMX8MN_CLK_USDHC3_ROOT,
307 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
308 clk_dm(IMX8MN_CLK_QSPI_ROOT,
309 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
310 clk_dm(IMX8MN_CLK_NAND_ROOT,
311 imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
312 clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
313 imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
314 "nand_usdhc_bus", base + 0x4300, 0,
315 &share_count_nand));
316 clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
317 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
318
319 /* clks not needed in SPL stage */
320 #ifndef CONFIG_SPL_BUILD
321 clk_dm(IMX8MN_CLK_ENET_REF,
322 imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
323 base + 0xa980));
324 clk_dm(IMX8MN_CLK_ENET_TIMER,
325 imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
326 base + 0xaa00));
327 clk_dm(IMX8MN_CLK_ENET_PHY_REF,
328 imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
329 base + 0xaa80));
330 clk_dm(IMX8MN_CLK_ENET1_ROOT,
331 imx_clk_gate4("enet1_root_clk", "enet_axi",
332 base + 0x40a0, 0));
333 #endif
334
335 #if CONFIG_IS_ENABLED(DM_SPI)
336 clk_dm(IMX8MN_CLK_ECSPI1,
337 imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
338 clk_dm(IMX8MN_CLK_ECSPI2,
339 imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
340 clk_dm(IMX8MN_CLK_ECSPI3,
341 imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
342 clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
343 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
344 clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
345 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
346 clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
347 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
348 #endif
349
350 return 0;
351 }
352
353 static const struct udevice_id imx8mn_clk_ids[] = {
354 { .compatible = "fsl,imx8mn-ccm" },
355 { },
356 };
357
358 U_BOOT_DRIVER(imx8mn_clk) = {
359 .name = "clk_imx8mn",
360 .id = UCLASS_CLK,
361 .of_match = imx8mn_clk_ids,
362 .ops = &ccf_clk_ops,
363 .probe = imx8mn_clk_probe,
364 .flags = DM_FLAG_PRE_RELOC,
365 };
366