1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2017-2019 NXP.
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <malloc.h>
11 #include <clk-uclass.h>
12 #include <dm/device.h>
13 #include <dm/devres.h>
14 #include <linux/bitops.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/iopoll.h>
19 #include <clk.h>
20 #include <div64.h>
21
22 #include "clk.h"
23
24 #define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
25 #define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
26
27 #define GNRL_CTL 0x0
28 #define DIV_CTL 0x4
29 #define LOCK_STATUS BIT(31)
30 #define LOCK_SEL_MASK BIT(29)
31 #define CLKE_MASK BIT(11)
32 #define RST_MASK BIT(9)
33 #define BYPASS_MASK BIT(4)
34 #define MDIV_SHIFT 12
35 #define MDIV_MASK GENMASK(21, 12)
36 #define PDIV_SHIFT 4
37 #define PDIV_MASK GENMASK(9, 4)
38 #define SDIV_SHIFT 0
39 #define SDIV_MASK GENMASK(2, 0)
40 #define KDIV_SHIFT 0
41 #define KDIV_MASK GENMASK(15, 0)
42
43 #define LOCK_TIMEOUT_US 10000
44
45 struct clk_pll14xx {
46 struct clk clk;
47 void __iomem *base;
48 enum imx_pll14xx_type type;
49 const struct imx_pll14xx_rate_table *rate_table;
50 int rate_count;
51 };
52
53 #define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
54
55 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
56 { \
57 .rate = (_rate), \
58 .mdiv = (_m), \
59 .pdiv = (_p), \
60 .sdiv = (_s), \
61 }
62
63 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
64 { \
65 .rate = (_rate), \
66 .mdiv = (_m), \
67 .pdiv = (_p), \
68 .sdiv = (_s), \
69 .kdiv = (_k), \
70 }
71
72 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
73 PLL_1416X_RATE(1800000000U, 225, 3, 0),
74 PLL_1416X_RATE(1600000000U, 200, 3, 0),
75 PLL_1416X_RATE(1500000000U, 375, 3, 1),
76 PLL_1416X_RATE(1400000000U, 350, 3, 1),
77 PLL_1416X_RATE(1200000000U, 300, 3, 1),
78 PLL_1416X_RATE(1000000000U, 250, 3, 1),
79 PLL_1416X_RATE(800000000U, 200, 3, 1),
80 PLL_1416X_RATE(750000000U, 250, 2, 2),
81 PLL_1416X_RATE(700000000U, 350, 3, 2),
82 PLL_1416X_RATE(600000000U, 300, 3, 2),
83 };
84
85 const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
86 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
87 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
88 PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
89 PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
90 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
91 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
92 };
93
94 struct imx_pll14xx_clk imx_1443x_pll __initdata = {
95 .type = PLL_1443X,
96 .rate_table = imx_pll1443x_tbl,
97 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
98 };
99 EXPORT_SYMBOL_GPL(imx_1443x_pll);
100
101 struct imx_pll14xx_clk imx_1443x_dram_pll __initdata = {
102 .type = PLL_1443X,
103 .rate_table = imx_pll1443x_tbl,
104 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
105 .flags = CLK_GET_RATE_NOCACHE,
106 };
107 EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
108
109 struct imx_pll14xx_clk imx_1416x_pll __initdata = {
110 .type = PLL_1416X,
111 .rate_table = imx_pll1416x_tbl,
112 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
113 };
114 EXPORT_SYMBOL_GPL(imx_1416x_pll);
115
imx_get_pll_settings(struct clk_pll14xx * pll,unsigned long rate)116 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
117 struct clk_pll14xx *pll, unsigned long rate)
118 {
119 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
120 int i;
121
122 for (i = 0; i < pll->rate_count; i++)
123 if (rate == rate_table[i].rate)
124 return &rate_table[i];
125
126 return NULL;
127 }
128
clk_pll1416x_recalc_rate(struct clk * clk)129 static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
130 {
131 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
132 u64 fvco = clk_get_parent_rate(clk);
133 u32 mdiv, pdiv, sdiv, pll_div;
134
135 pll_div = readl(pll->base + 4);
136 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
137 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
138 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
139
140 fvco *= mdiv;
141 do_div(fvco, pdiv << sdiv);
142
143 return fvco;
144 }
145
clk_pll1443x_recalc_rate(struct clk * clk)146 static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
147 {
148 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
149 u64 fvco = clk_get_parent_rate(clk);
150 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
151 short int kdiv;
152
153 pll_div_ctl0 = readl(pll->base + 4);
154 pll_div_ctl1 = readl(pll->base + 8);
155 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
156 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
157 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
158 kdiv = pll_div_ctl1 & KDIV_MASK;
159
160 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
161 fvco *= (mdiv * 65536 + kdiv);
162 pdiv *= 65536;
163
164 do_div(fvco, pdiv << sdiv);
165
166 return fvco;
167 }
168
clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table * rate,u32 pll_div)169 static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
170 u32 pll_div)
171 {
172 u32 old_mdiv, old_pdiv;
173
174 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
175 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
176
177 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
178 }
179
clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table * rate,u32 pll_div_ctl0,u32 pll_div_ctl1)180 static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
181 u32 pll_div_ctl0, u32 pll_div_ctl1)
182 {
183 u32 old_mdiv, old_pdiv, old_kdiv;
184
185 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
186 old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
187 old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
188
189 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
190 rate->kdiv != old_kdiv;
191 }
192
clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table * rate,u32 pll_div_ctl0,u32 pll_div_ctl1)193 static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
194 u32 pll_div_ctl0, u32 pll_div_ctl1)
195 {
196 u32 old_mdiv, old_pdiv, old_kdiv;
197
198 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
199 old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
200 old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
201
202 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
203 rate->kdiv != old_kdiv;
204 }
205
clk_pll14xx_wait_lock(struct clk_pll14xx * pll)206 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
207 {
208 u32 val;
209
210 return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
211 LOCK_TIMEOUT_US);
212 }
213
clk_pll1416x_set_rate(struct clk * clk,unsigned long drate)214 static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
215 {
216 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
217 const struct imx_pll14xx_rate_table *rate;
218 u32 tmp, div_val;
219 int ret;
220
221 rate = imx_get_pll_settings(pll, drate);
222 if (!rate) {
223 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
224 drate, "xxxx");
225 return -EINVAL;
226 }
227
228 tmp = readl(pll->base + 4);
229
230 if (!clk_pll1416x_mp_change(rate, tmp)) {
231 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
232 tmp |= rate->sdiv << SDIV_SHIFT;
233 writel(tmp, pll->base + 4);
234
235 return clk_pll1416x_recalc_rate(clk);
236 }
237
238 /* Bypass clock and set lock to pll output lock */
239 tmp = readl(pll->base);
240 tmp |= LOCK_SEL_MASK;
241 writel(tmp, pll->base);
242
243 /* Enable RST */
244 tmp &= ~RST_MASK;
245 writel(tmp, pll->base);
246
247 /* Enable BYPASS */
248 tmp |= BYPASS_MASK;
249 writel(tmp, pll->base);
250
251
252 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
253 (rate->sdiv << SDIV_SHIFT);
254 writel(div_val, pll->base + 0x4);
255
256 /*
257 * According to SPEC, t3 - t2 need to be greater than
258 * 1us and 1/FREF, respectively.
259 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
260 * 3us.
261 */
262 udelay(3);
263
264 /* Disable RST */
265 tmp |= RST_MASK;
266 writel(tmp, pll->base);
267
268 /* Wait Lock */
269 ret = clk_pll14xx_wait_lock(pll);
270 if (ret)
271 return ret;
272
273 /* Bypass */
274 tmp &= ~BYPASS_MASK;
275 writel(tmp, pll->base);
276
277 return clk_pll1416x_recalc_rate(clk);
278 }
279
clk_pll1443x_set_rate(struct clk * clk,unsigned long drate)280 static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
281 {
282 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
283 const struct imx_pll14xx_rate_table *rate;
284 u32 tmp, div_val;
285 int ret;
286
287 rate = imx_get_pll_settings(pll, drate);
288 if (!rate) {
289 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
290 drate, "===");
291 return -EINVAL;
292 }
293
294 tmp = readl(pll->base + 4);
295 div_val = readl(pll->base + 8);
296
297 if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
298 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
299 tmp |= rate->sdiv << SDIV_SHIFT;
300 writel(tmp, pll->base + 4);
301
302 return clk_pll1443x_recalc_rate(clk);
303 }
304
305 tmp = readl(pll->base);
306
307 /* Enable RST */
308 tmp &= ~RST_MASK;
309 writel(tmp, pll->base);
310
311 /* Enable BYPASS */
312 tmp |= BYPASS_MASK;
313 writel(tmp, pll->base);
314
315 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
316 (rate->sdiv << SDIV_SHIFT);
317 writel(div_val, pll->base + 0x4);
318 writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
319
320 /*
321 * According to SPEC, t3 - t2 need to be greater than
322 * 1us and 1/FREF, respectively.
323 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
324 * 3us.
325 */
326 udelay(3);
327
328 /* Disable RST */
329 tmp |= RST_MASK;
330 writel(tmp, pll->base);
331
332 /* Wait Lock*/
333 ret = clk_pll14xx_wait_lock(pll);
334 if (ret)
335 return ret;
336
337 /* Bypass */
338 tmp &= ~BYPASS_MASK;
339 writel(tmp, pll->base);
340
341 return clk_pll1443x_recalc_rate(clk);
342 }
343
clk_pll14xx_prepare(struct clk * clk)344 static int clk_pll14xx_prepare(struct clk *clk)
345 {
346 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
347 u32 val;
348
349 /*
350 * RESETB = 1 from 0, PLL starts its normal
351 * operation after lock time
352 */
353 val = readl(pll->base + GNRL_CTL);
354 val |= RST_MASK;
355 writel(val, pll->base + GNRL_CTL);
356
357 return clk_pll14xx_wait_lock(pll);
358 }
359
clk_pll14xx_unprepare(struct clk * clk)360 static int clk_pll14xx_unprepare(struct clk *clk)
361 {
362 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
363 u32 val;
364
365 /*
366 * Set RST to 0, power down mode is enabled and
367 * every digital block is reset
368 */
369 val = readl(pll->base + GNRL_CTL);
370 val &= ~RST_MASK;
371 writel(val, pll->base + GNRL_CTL);
372
373 return 0;
374 }
375
376 static const struct clk_ops clk_pll1416x_ops = {
377 .enable = clk_pll14xx_prepare,
378 .disable = clk_pll14xx_unprepare,
379 .set_rate = clk_pll1416x_set_rate,
380 .get_rate = clk_pll1416x_recalc_rate,
381 };
382
383 static const struct clk_ops clk_pll1443x_ops = {
384 .enable = clk_pll14xx_prepare,
385 .disable = clk_pll14xx_unprepare,
386 .set_rate = clk_pll1443x_set_rate,
387 .get_rate = clk_pll1443x_recalc_rate,
388 };
389
imx_clk_pll14xx(const char * name,const char * parent_name,void __iomem * base,const struct imx_pll14xx_clk * pll_clk)390 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
391 void __iomem *base,
392 const struct imx_pll14xx_clk *pll_clk)
393 {
394 struct clk_pll14xx *pll;
395 struct clk *clk;
396 char *type_name;
397 int ret;
398
399 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
400 if (!pll)
401 return ERR_PTR(-ENOMEM);
402
403 switch (pll_clk->type) {
404 case PLL_1416X:
405 type_name = UBOOT_DM_CLK_IMX_PLL1416X;
406 break;
407 case PLL_1443X:
408 type_name = UBOOT_DM_CLK_IMX_PLL1443X;
409 break;
410 default:
411 pr_err("%s: Unknown pll type for pll clk %s\n",
412 __func__, name);
413 return ERR_PTR(-EINVAL);
414 };
415
416 pll->base = base;
417 pll->type = pll_clk->type;
418 pll->rate_table = pll_clk->rate_table;
419 pll->rate_count = pll_clk->rate_count;
420
421 clk = &pll->clk;
422
423 ret = clk_register(clk, type_name, name, parent_name);
424 if (ret) {
425 pr_err("%s: failed to register pll %s %d\n",
426 __func__, name, ret);
427 kfree(pll);
428 return ERR_PTR(ret);
429 }
430
431 return clk;
432 }
433
434 U_BOOT_DRIVER(clk_pll1443x) = {
435 .name = UBOOT_DM_CLK_IMX_PLL1443X,
436 .id = UCLASS_CLK,
437 .ops = &clk_pll1443x_ops,
438 .flags = DM_FLAG_PRE_RELOC,
439 };
440
441 U_BOOT_DRIVER(clk_pll1416x) = {
442 .name = UBOOT_DM_CLK_IMX_PLL1416X,
443 .id = UCLASS_CLK,
444 .ops = &clk_pll1416x_ops,
445 .flags = DM_FLAG_PRE_RELOC,
446 };
447