1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY UCLASS_CLK
7
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <div64.h>
11 #include <dm.h>
12 #include <init.h>
13 #include <log.h>
14 #include <regmap.h>
15 #include <spl.h>
16 #include <syscon.h>
17 #include <time.h>
18 #include <vsprintf.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/global_data.h>
21 #include <dm/device_compat.h>
22 #include <dt-bindings/clock/stm32mp1-clks.h>
23 #include <dt-bindings/clock/stm32mp1-clksrc.h>
24 #include <linux/bitops.h>
25 #include <linux/io.h>
26 #include <linux/iopoll.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #if defined(CONFIG_SPL_BUILD)
31 /* activate clock tree initialization in the driver */
32 #define STM32MP1_CLOCK_TREE_INIT
33 #endif
34
35 #define MAX_HSI_HZ 64000000
36
37 /* TIMEOUT */
38 #define TIMEOUT_200MS 200000
39 #define TIMEOUT_1S 1000000
40
41 /* STGEN registers */
42 #define STGENC_CNTCR 0x00
43 #define STGENC_CNTSR 0x04
44 #define STGENC_CNTCVL 0x08
45 #define STGENC_CNTCVU 0x0C
46 #define STGENC_CNTFID0 0x20
47
48 #define STGENC_CNTCR_EN BIT(0)
49
50 /* RCC registers */
51 #define RCC_OCENSETR 0x0C
52 #define RCC_OCENCLRR 0x10
53 #define RCC_HSICFGR 0x18
54 #define RCC_MPCKSELR 0x20
55 #define RCC_ASSCKSELR 0x24
56 #define RCC_RCK12SELR 0x28
57 #define RCC_MPCKDIVR 0x2C
58 #define RCC_AXIDIVR 0x30
59 #define RCC_APB4DIVR 0x3C
60 #define RCC_APB5DIVR 0x40
61 #define RCC_RTCDIVR 0x44
62 #define RCC_MSSCKSELR 0x48
63 #define RCC_PLL1CR 0x80
64 #define RCC_PLL1CFGR1 0x84
65 #define RCC_PLL1CFGR2 0x88
66 #define RCC_PLL1FRACR 0x8C
67 #define RCC_PLL1CSGR 0x90
68 #define RCC_PLL2CR 0x94
69 #define RCC_PLL2CFGR1 0x98
70 #define RCC_PLL2CFGR2 0x9C
71 #define RCC_PLL2FRACR 0xA0
72 #define RCC_PLL2CSGR 0xA4
73 #define RCC_I2C46CKSELR 0xC0
74 #define RCC_SPI6CKSELR 0xC4
75 #define RCC_CPERCKSELR 0xD0
76 #define RCC_STGENCKSELR 0xD4
77 #define RCC_DDRITFCR 0xD8
78 #define RCC_BDCR 0x140
79 #define RCC_RDLSICR 0x144
80 #define RCC_MP_APB4ENSETR 0x200
81 #define RCC_MP_APB5ENSETR 0x208
82 #define RCC_MP_AHB5ENSETR 0x210
83 #define RCC_MP_AHB6ENSETR 0x218
84 #define RCC_OCRDYR 0x808
85 #define RCC_DBGCFGR 0x80C
86 #define RCC_RCK3SELR 0x820
87 #define RCC_RCK4SELR 0x824
88 #define RCC_MCUDIVR 0x830
89 #define RCC_APB1DIVR 0x834
90 #define RCC_APB2DIVR 0x838
91 #define RCC_APB3DIVR 0x83C
92 #define RCC_PLL3CR 0x880
93 #define RCC_PLL3CFGR1 0x884
94 #define RCC_PLL3CFGR2 0x888
95 #define RCC_PLL3FRACR 0x88C
96 #define RCC_PLL3CSGR 0x890
97 #define RCC_PLL4CR 0x894
98 #define RCC_PLL4CFGR1 0x898
99 #define RCC_PLL4CFGR2 0x89C
100 #define RCC_PLL4FRACR 0x8A0
101 #define RCC_PLL4CSGR 0x8A4
102 #define RCC_I2C12CKSELR 0x8C0
103 #define RCC_I2C35CKSELR 0x8C4
104 #define RCC_SPI2S1CKSELR 0x8D8
105 #define RCC_SPI2S23CKSELR 0x8DC
106 #define RCC_SPI45CKSELR 0x8E0
107 #define RCC_UART6CKSELR 0x8E4
108 #define RCC_UART24CKSELR 0x8E8
109 #define RCC_UART35CKSELR 0x8EC
110 #define RCC_UART78CKSELR 0x8F0
111 #define RCC_SDMMC12CKSELR 0x8F4
112 #define RCC_SDMMC3CKSELR 0x8F8
113 #define RCC_ETHCKSELR 0x8FC
114 #define RCC_QSPICKSELR 0x900
115 #define RCC_FMCCKSELR 0x904
116 #define RCC_USBCKSELR 0x91C
117 #define RCC_DSICKSELR 0x924
118 #define RCC_ADCCKSELR 0x928
119 #define RCC_MP_APB1ENSETR 0xA00
120 #define RCC_MP_APB2ENSETR 0XA08
121 #define RCC_MP_APB3ENSETR 0xA10
122 #define RCC_MP_AHB2ENSETR 0xA18
123 #define RCC_MP_AHB3ENSETR 0xA20
124 #define RCC_MP_AHB4ENSETR 0xA28
125
126 /* used for most of SELR register */
127 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
128 #define RCC_SELR_SRCRDY BIT(31)
129
130 /* Values of RCC_MPCKSELR register */
131 #define RCC_MPCKSELR_HSI 0
132 #define RCC_MPCKSELR_HSE 1
133 #define RCC_MPCKSELR_PLL 2
134 #define RCC_MPCKSELR_PLL_MPUDIV 3
135
136 /* Values of RCC_ASSCKSELR register */
137 #define RCC_ASSCKSELR_HSI 0
138 #define RCC_ASSCKSELR_HSE 1
139 #define RCC_ASSCKSELR_PLL 2
140
141 /* Values of RCC_MSSCKSELR register */
142 #define RCC_MSSCKSELR_HSI 0
143 #define RCC_MSSCKSELR_HSE 1
144 #define RCC_MSSCKSELR_CSI 2
145 #define RCC_MSSCKSELR_PLL 3
146
147 /* Values of RCC_CPERCKSELR register */
148 #define RCC_CPERCKSELR_HSI 0
149 #define RCC_CPERCKSELR_CSI 1
150 #define RCC_CPERCKSELR_HSE 2
151
152 /* used for most of DIVR register : max div for RTC */
153 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
154 #define RCC_DIVR_DIVRDY BIT(31)
155
156 /* Masks for specific DIVR registers */
157 #define RCC_APBXDIV_MASK GENMASK(2, 0)
158 #define RCC_MPUDIV_MASK GENMASK(2, 0)
159 #define RCC_AXIDIV_MASK GENMASK(2, 0)
160 #define RCC_MCUDIV_MASK GENMASK(3, 0)
161
162 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
163 #define RCC_MP_ENCLRR_OFFSET 4
164
165 /* Fields of RCC_BDCR register */
166 #define RCC_BDCR_LSEON BIT(0)
167 #define RCC_BDCR_LSEBYP BIT(1)
168 #define RCC_BDCR_LSERDY BIT(2)
169 #define RCC_BDCR_DIGBYP BIT(3)
170 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
171 #define RCC_BDCR_LSEDRV_SHIFT 4
172 #define RCC_BDCR_LSECSSON BIT(8)
173 #define RCC_BDCR_RTCCKEN BIT(20)
174 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
175 #define RCC_BDCR_RTCSRC_SHIFT 16
176
177 /* Fields of RCC_RDLSICR register */
178 #define RCC_RDLSICR_LSION BIT(0)
179 #define RCC_RDLSICR_LSIRDY BIT(1)
180
181 /* used for ALL PLLNCR registers */
182 #define RCC_PLLNCR_PLLON BIT(0)
183 #define RCC_PLLNCR_PLLRDY BIT(1)
184 #define RCC_PLLNCR_SSCG_CTRL BIT(2)
185 #define RCC_PLLNCR_DIVPEN BIT(4)
186 #define RCC_PLLNCR_DIVQEN BIT(5)
187 #define RCC_PLLNCR_DIVREN BIT(6)
188 #define RCC_PLLNCR_DIVEN_SHIFT 4
189
190 /* used for ALL PLLNCFGR1 registers */
191 #define RCC_PLLNCFGR1_DIVM_SHIFT 16
192 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
193 #define RCC_PLLNCFGR1_DIVN_SHIFT 0
194 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
195 /* only for PLL3 and PLL4 */
196 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
197 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
198
199 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
200 #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
201 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
202 #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
203 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
204 #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
205 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
206 #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
207 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
208
209 /* used for ALL PLLNFRACR registers */
210 #define RCC_PLLNFRACR_FRACV_SHIFT 3
211 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
212 #define RCC_PLLNFRACR_FRACLE BIT(16)
213
214 /* used for ALL PLLNCSGR registers */
215 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
216 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
217 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
218 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
219 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
220 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
221
222 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
223 #define RCC_OCENR_HSION BIT(0)
224 #define RCC_OCENR_CSION BIT(4)
225 #define RCC_OCENR_DIGBYP BIT(7)
226 #define RCC_OCENR_HSEON BIT(8)
227 #define RCC_OCENR_HSEBYP BIT(10)
228 #define RCC_OCENR_HSECSSON BIT(11)
229
230 /* Fields of RCC_OCRDYR register */
231 #define RCC_OCRDYR_HSIRDY BIT(0)
232 #define RCC_OCRDYR_HSIDIVRDY BIT(2)
233 #define RCC_OCRDYR_CSIRDY BIT(4)
234 #define RCC_OCRDYR_HSERDY BIT(8)
235
236 /* Fields of DDRITFCR register */
237 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
238 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
239 #define RCC_DDRITFCR_DDRCKMOD_SSR 0
240
241 /* Fields of RCC_HSICFGR register */
242 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
243
244 /* used for MCO related operations */
245 #define RCC_MCOCFG_MCOON BIT(12)
246 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
247 #define RCC_MCOCFG_MCODIV_SHIFT 4
248 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
249
250 enum stm32mp1_parent_id {
251 /*
252 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
253 * they are used as index in osc_clk[] as clock reference
254 */
255 _HSI,
256 _HSE,
257 _CSI,
258 _LSI,
259 _LSE,
260 _I2S_CKIN,
261 NB_OSC,
262
263 /* other parent source */
264 _HSI_KER = NB_OSC,
265 _HSE_KER,
266 _HSE_KER_DIV2,
267 _CSI_KER,
268 _PLL1_P,
269 _PLL1_Q,
270 _PLL1_R,
271 _PLL2_P,
272 _PLL2_Q,
273 _PLL2_R,
274 _PLL3_P,
275 _PLL3_Q,
276 _PLL3_R,
277 _PLL4_P,
278 _PLL4_Q,
279 _PLL4_R,
280 _ACLK,
281 _PCLK1,
282 _PCLK2,
283 _PCLK3,
284 _PCLK4,
285 _PCLK5,
286 _HCLK6,
287 _HCLK2,
288 _CK_PER,
289 _CK_MPU,
290 _CK_MCU,
291 _DSI_PHY,
292 _USB_PHY_48,
293 _PARENT_NB,
294 _UNKNOWN_ID = 0xff,
295 };
296
297 enum stm32mp1_parent_sel {
298 _I2C12_SEL,
299 _I2C35_SEL,
300 _I2C46_SEL,
301 _UART6_SEL,
302 _UART24_SEL,
303 _UART35_SEL,
304 _UART78_SEL,
305 _SDMMC12_SEL,
306 _SDMMC3_SEL,
307 _ETH_SEL,
308 _QSPI_SEL,
309 _FMC_SEL,
310 _USBPHY_SEL,
311 _USBO_SEL,
312 _STGEN_SEL,
313 _DSI_SEL,
314 _ADC12_SEL,
315 _SPI1_SEL,
316 _SPI23_SEL,
317 _SPI45_SEL,
318 _SPI6_SEL,
319 _RTC_SEL,
320 _PARENT_SEL_NB,
321 _UNKNOWN_SEL = 0xff,
322 };
323
324 enum stm32mp1_pll_id {
325 _PLL1,
326 _PLL2,
327 _PLL3,
328 _PLL4,
329 _PLL_NB
330 };
331
332 enum stm32mp1_div_id {
333 _DIV_P,
334 _DIV_Q,
335 _DIV_R,
336 _DIV_NB,
337 };
338
339 enum stm32mp1_clksrc_id {
340 CLKSRC_MPU,
341 CLKSRC_AXI,
342 CLKSRC_MCU,
343 CLKSRC_PLL12,
344 CLKSRC_PLL3,
345 CLKSRC_PLL4,
346 CLKSRC_RTC,
347 CLKSRC_MCO1,
348 CLKSRC_MCO2,
349 CLKSRC_NB
350 };
351
352 enum stm32mp1_clkdiv_id {
353 CLKDIV_MPU,
354 CLKDIV_AXI,
355 CLKDIV_MCU,
356 CLKDIV_APB1,
357 CLKDIV_APB2,
358 CLKDIV_APB3,
359 CLKDIV_APB4,
360 CLKDIV_APB5,
361 CLKDIV_RTC,
362 CLKDIV_MCO1,
363 CLKDIV_MCO2,
364 CLKDIV_NB
365 };
366
367 enum stm32mp1_pllcfg {
368 PLLCFG_M,
369 PLLCFG_N,
370 PLLCFG_P,
371 PLLCFG_Q,
372 PLLCFG_R,
373 PLLCFG_O,
374 PLLCFG_NB
375 };
376
377 enum stm32mp1_pllcsg {
378 PLLCSG_MOD_PER,
379 PLLCSG_INC_STEP,
380 PLLCSG_SSCG_MODE,
381 PLLCSG_NB
382 };
383
384 enum stm32mp1_plltype {
385 PLL_800,
386 PLL_1600,
387 PLL_TYPE_NB
388 };
389
390 struct stm32mp1_pll {
391 u8 refclk_min;
392 u8 refclk_max;
393 u8 divn_max;
394 };
395
396 struct stm32mp1_clk_gate {
397 u16 offset;
398 u8 bit;
399 u8 index;
400 u8 set_clr;
401 u8 sel;
402 u8 fixed;
403 };
404
405 struct stm32mp1_clk_sel {
406 u16 offset;
407 u8 src;
408 u8 msk;
409 u8 nb_parent;
410 const u8 *parent;
411 };
412
413 #define REFCLK_SIZE 4
414 struct stm32mp1_clk_pll {
415 enum stm32mp1_plltype plltype;
416 u16 rckxselr;
417 u16 pllxcfgr1;
418 u16 pllxcfgr2;
419 u16 pllxfracr;
420 u16 pllxcr;
421 u16 pllxcsgr;
422 u8 refclk[REFCLK_SIZE];
423 };
424
425 struct stm32mp1_clk_data {
426 const struct stm32mp1_clk_gate *gate;
427 const struct stm32mp1_clk_sel *sel;
428 const struct stm32mp1_clk_pll *pll;
429 const int nb_gate;
430 };
431
432 struct stm32mp1_clk_priv {
433 fdt_addr_t base;
434 const struct stm32mp1_clk_data *data;
435 struct clk osc_clk[NB_OSC];
436 };
437
438 #define STM32MP1_CLK(off, b, idx, s) \
439 { \
440 .offset = (off), \
441 .bit = (b), \
442 .index = (idx), \
443 .set_clr = 0, \
444 .sel = (s), \
445 .fixed = _UNKNOWN_ID, \
446 }
447
448 #define STM32MP1_CLK_F(off, b, idx, f) \
449 { \
450 .offset = (off), \
451 .bit = (b), \
452 .index = (idx), \
453 .set_clr = 0, \
454 .sel = _UNKNOWN_SEL, \
455 .fixed = (f), \
456 }
457
458 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
459 { \
460 .offset = (off), \
461 .bit = (b), \
462 .index = (idx), \
463 .set_clr = 1, \
464 .sel = (s), \
465 .fixed = _UNKNOWN_ID, \
466 }
467
468 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
469 { \
470 .offset = (off), \
471 .bit = (b), \
472 .index = (idx), \
473 .set_clr = 1, \
474 .sel = _UNKNOWN_SEL, \
475 .fixed = (f), \
476 }
477
478 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
479 [(idx)] = { \
480 .offset = (off), \
481 .src = (s), \
482 .msk = (m), \
483 .parent = (p), \
484 .nb_parent = ARRAY_SIZE((p)) \
485 }
486
487 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
488 p1, p2, p3, p4) \
489 [(idx)] = { \
490 .plltype = (type), \
491 .rckxselr = (off1), \
492 .pllxcfgr1 = (off2), \
493 .pllxcfgr2 = (off3), \
494 .pllxfracr = (off4), \
495 .pllxcr = (off5), \
496 .pllxcsgr = (off6), \
497 .refclk[0] = (p1), \
498 .refclk[1] = (p2), \
499 .refclk[2] = (p3), \
500 .refclk[3] = (p4), \
501 }
502
503 static const u8 stm32mp1_clks[][2] = {
504 {CK_PER, _CK_PER},
505 {CK_MPU, _CK_MPU},
506 {CK_AXI, _ACLK},
507 {CK_MCU, _CK_MCU},
508 {CK_HSE, _HSE},
509 {CK_CSI, _CSI},
510 {CK_LSI, _LSI},
511 {CK_LSE, _LSE},
512 {CK_HSI, _HSI},
513 {CK_HSE_DIV2, _HSE_KER_DIV2},
514 };
515
516 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
517 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
518 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
519 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
520 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
521 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
522 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
523 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
524 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
525 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
526 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
527 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
528
529 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 11, SPI2_K, _SPI23_SEL),
530 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 12, SPI3_K, _SPI23_SEL),
531 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
532 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
533 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
534 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
535 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
536 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
537 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
538 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
539 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
540 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
541
542 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
543 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 9, SPI4_K, _SPI45_SEL),
544 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
546
547 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
548 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
549
550 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
551 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
552 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
553 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
554 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
555 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
556
557 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
558 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
559 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
560 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
561 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
562 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
563
564 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
565 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
566 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
567 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
568
569 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
570 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
571
572 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
573 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
574 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
575 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
576 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
577 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
578 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
579 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
580 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
581 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
582 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
583
584 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
585 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
586
587 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
588 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
589 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
590 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
591 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
592 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
593 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
594 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
595 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
596
597 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
598
599 STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
600 };
601
602 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
603 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
604 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
605 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
606 _HSE_KER};
607 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
608 _HSE_KER};
609 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
610 _HSE_KER};
611 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
612 _HSE_KER};
613 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
614 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
615 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
616 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
617 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
618 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
619 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
620 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
621 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
622 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
623 /* same parents for SPI1=RCC_SPI2S1CKSELR and SPI2&3 = RCC_SPI2S23CKSELR */
624 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
625 _PLL3_R};
626 static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
627 _HSE_KER};
628 static const u8 spi6_parents[] = {_PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER,
629 _HSE_KER, _PLL3_Q};
630 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
631
632 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
633 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
634 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
635 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
636 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
637 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
638 uart24_parents),
639 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
640 uart35_parents),
641 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
642 uart78_parents),
643 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
644 sdmmc12_parents),
645 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
646 sdmmc3_parents),
647 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
648 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
649 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
650 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
651 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
652 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
653 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
654 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
655 STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
656 STM32MP1_CLK_PARENT(_SPI23_SEL, RCC_SPI2S23CKSELR, 0, 0x7, spi_parents),
657 STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
658 STM32MP1_CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
659 STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
660 (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
661 rtc_parents),
662 };
663
664 #ifdef STM32MP1_CLOCK_TREE_INIT
665
666 /* define characteristic of PLL according type */
667 #define DIVM_MIN 0
668 #define DIVM_MAX 63
669 #define DIVN_MIN 24
670 #define DIVP_MIN 0
671 #define DIVP_MAX 127
672 #define FRAC_MAX 8192
673
674 #define PLL1600_VCO_MIN 800000000
675 #define PLL1600_VCO_MAX 1600000000
676
677 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
678 [PLL_800] = {
679 .refclk_min = 4,
680 .refclk_max = 16,
681 .divn_max = 99,
682 },
683 [PLL_1600] = {
684 .refclk_min = 8,
685 .refclk_max = 16,
686 .divn_max = 199,
687 },
688 };
689 #endif /* STM32MP1_CLOCK_TREE_INIT */
690
691 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
692 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
693 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
694 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
695 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
696 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
697 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
698 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
699 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
700 STM32MP1_CLK_PLL(_PLL3, PLL_800,
701 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
702 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
703 _HSI, _HSE, _CSI, _UNKNOWN_ID),
704 STM32MP1_CLK_PLL(_PLL4, PLL_800,
705 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
706 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
707 _HSI, _HSE, _CSI, _I2S_CKIN),
708 };
709
710 /* Prescaler table lookups for clock computation */
711 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
712 static const u8 stm32mp1_mcu_div[16] = {
713 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
714 };
715
716 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
717 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
718 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
719 static const u8 stm32mp1_mpu_apbx_div[8] = {
720 0, 1, 2, 3, 4, 4, 4, 4
721 };
722
723 /* div = /1 /2 /3 /4 */
724 static const u8 stm32mp1_axi_div[8] = {
725 1, 2, 3, 4, 4, 4, 4, 4
726 };
727
728 static const __maybe_unused
729 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
730 [_HSI] = "HSI",
731 [_HSE] = "HSE",
732 [_CSI] = "CSI",
733 [_LSI] = "LSI",
734 [_LSE] = "LSE",
735 [_I2S_CKIN] = "I2S_CKIN",
736 [_HSI_KER] = "HSI_KER",
737 [_HSE_KER] = "HSE_KER",
738 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
739 [_CSI_KER] = "CSI_KER",
740 [_PLL1_P] = "PLL1_P",
741 [_PLL1_Q] = "PLL1_Q",
742 [_PLL1_R] = "PLL1_R",
743 [_PLL2_P] = "PLL2_P",
744 [_PLL2_Q] = "PLL2_Q",
745 [_PLL2_R] = "PLL2_R",
746 [_PLL3_P] = "PLL3_P",
747 [_PLL3_Q] = "PLL3_Q",
748 [_PLL3_R] = "PLL3_R",
749 [_PLL4_P] = "PLL4_P",
750 [_PLL4_Q] = "PLL4_Q",
751 [_PLL4_R] = "PLL4_R",
752 [_ACLK] = "ACLK",
753 [_PCLK1] = "PCLK1",
754 [_PCLK2] = "PCLK2",
755 [_PCLK3] = "PCLK3",
756 [_PCLK4] = "PCLK4",
757 [_PCLK5] = "PCLK5",
758 [_HCLK6] = "KCLK6",
759 [_HCLK2] = "HCLK2",
760 [_CK_PER] = "CK_PER",
761 [_CK_MPU] = "CK_MPU",
762 [_CK_MCU] = "CK_MCU",
763 [_USB_PHY_48] = "USB_PHY_48",
764 [_DSI_PHY] = "DSI_PHY_PLL",
765 };
766
767 static const __maybe_unused
768 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
769 [_I2C12_SEL] = "I2C12",
770 [_I2C35_SEL] = "I2C35",
771 [_I2C46_SEL] = "I2C46",
772 [_UART6_SEL] = "UART6",
773 [_UART24_SEL] = "UART24",
774 [_UART35_SEL] = "UART35",
775 [_UART78_SEL] = "UART78",
776 [_SDMMC12_SEL] = "SDMMC12",
777 [_SDMMC3_SEL] = "SDMMC3",
778 [_ETH_SEL] = "ETH",
779 [_QSPI_SEL] = "QSPI",
780 [_FMC_SEL] = "FMC",
781 [_USBPHY_SEL] = "USBPHY",
782 [_USBO_SEL] = "USBO",
783 [_STGEN_SEL] = "STGEN",
784 [_DSI_SEL] = "DSI",
785 [_ADC12_SEL] = "ADC12",
786 [_SPI1_SEL] = "SPI1",
787 [_SPI45_SEL] = "SPI45",
788 [_RTC_SEL] = "RTC",
789 };
790
791 static const struct stm32mp1_clk_data stm32mp1_data = {
792 .gate = stm32mp1_clk_gate,
793 .sel = stm32mp1_clk_sel,
794 .pll = stm32mp1_clk_pll,
795 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
796 };
797
stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv * priv,int idx)798 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
799 {
800 if (idx >= NB_OSC) {
801 log_debug("clk id %d not found\n", idx);
802 return 0;
803 }
804
805 return clk_get_rate(&priv->osc_clk[idx]);
806 }
807
stm32mp1_clk_get_id(struct stm32mp1_clk_priv * priv,unsigned long id)808 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
809 {
810 const struct stm32mp1_clk_gate *gate = priv->data->gate;
811 int i, nb_clks = priv->data->nb_gate;
812
813 for (i = 0; i < nb_clks; i++) {
814 if (gate[i].index == id)
815 break;
816 }
817
818 if (i == nb_clks) {
819 log_err("clk id %d not found\n", (u32)id);
820 return -EINVAL;
821 }
822
823 return i;
824 }
825
stm32mp1_clk_get_sel(struct stm32mp1_clk_priv * priv,int i)826 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
827 int i)
828 {
829 const struct stm32mp1_clk_gate *gate = priv->data->gate;
830
831 if (gate[i].sel > _PARENT_SEL_NB) {
832 log_err("parents for clk id %d not found\n", i);
833 return -EINVAL;
834 }
835
836 return gate[i].sel;
837 }
838
stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv * priv,int i)839 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
840 int i)
841 {
842 const struct stm32mp1_clk_gate *gate = priv->data->gate;
843
844 if (gate[i].fixed == _UNKNOWN_ID)
845 return -ENOENT;
846
847 return gate[i].fixed;
848 }
849
stm32mp1_clk_get_parent(struct stm32mp1_clk_priv * priv,unsigned long id)850 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
851 unsigned long id)
852 {
853 const struct stm32mp1_clk_sel *sel = priv->data->sel;
854 int i;
855 int s, p;
856 unsigned int idx;
857
858 for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
859 if (stm32mp1_clks[idx][0] == id)
860 return stm32mp1_clks[idx][1];
861
862 i = stm32mp1_clk_get_id(priv, id);
863 if (i < 0)
864 return i;
865
866 p = stm32mp1_clk_get_fixed_parent(priv, i);
867 if (p >= 0 && p < _PARENT_NB)
868 return p;
869
870 s = stm32mp1_clk_get_sel(priv, i);
871 if (s < 0)
872 return s;
873
874 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
875
876 if (p < sel[s].nb_parent) {
877 log_content("%s clock is the parent %s of clk id %d\n",
878 stm32mp1_clk_parent_name[sel[s].parent[p]],
879 stm32mp1_clk_parent_sel_name[s],
880 (u32)id);
881 return sel[s].parent[p];
882 }
883
884 log_err("no parents defined for clk id %d\n", (u32)id);
885
886 return -EINVAL;
887 }
888
pll_get_fref_ck(struct stm32mp1_clk_priv * priv,int pll_id)889 static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
890 int pll_id)
891 {
892 const struct stm32mp1_clk_pll *pll = priv->data->pll;
893 u32 selr;
894 int src;
895 ulong refclk;
896
897 /* Get current refclk */
898 selr = readl(priv->base + pll[pll_id].rckxselr);
899 src = selr & RCC_SELR_SRC_MASK;
900
901 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
902
903 return refclk;
904 }
905
906 /*
907 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
908 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
909 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
910 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
911 */
pll_get_fvco(struct stm32mp1_clk_priv * priv,int pll_id)912 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
913 int pll_id)
914 {
915 const struct stm32mp1_clk_pll *pll = priv->data->pll;
916 int divm, divn;
917 ulong refclk, fvco;
918 u32 cfgr1, fracr;
919
920 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
921 fracr = readl(priv->base + pll[pll_id].pllxfracr);
922
923 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
924 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
925
926 refclk = pll_get_fref_ck(priv, pll_id);
927
928 /* with FRACV :
929 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
930 * without FRACV
931 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
932 */
933 if (fracr & RCC_PLLNFRACR_FRACLE) {
934 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
935 >> RCC_PLLNFRACR_FRACV_SHIFT;
936 fvco = (ulong)lldiv((unsigned long long)refclk *
937 (((divn + 1) << 13) + fracv),
938 ((unsigned long long)(divm + 1)) << 13);
939 } else {
940 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
941 }
942
943 return fvco;
944 }
945
stm32mp1_read_pll_freq(struct stm32mp1_clk_priv * priv,int pll_id,int div_id)946 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
947 int pll_id, int div_id)
948 {
949 const struct stm32mp1_clk_pll *pll = priv->data->pll;
950 int divy;
951 ulong dfout;
952 u32 cfgr2;
953
954 if (div_id >= _DIV_NB)
955 return 0;
956
957 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
958 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
959
960 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
961
962 return dfout;
963 }
964
stm32mp1_clk_get_by_name(const char * name)965 static ulong stm32mp1_clk_get_by_name(const char *name)
966 {
967 struct clk clk;
968 struct udevice *dev = NULL;
969 ulong clock = 0;
970
971 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
972 if (clk_request(dev, &clk)) {
973 log_err("%s request", name);
974 } else {
975 clk.id = 0;
976 clock = clk_get_rate(&clk);
977 }
978 }
979
980 return clock;
981 }
982
stm32mp1_clk_get(struct stm32mp1_clk_priv * priv,int p)983 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
984 {
985 u32 reg;
986 ulong clock = 0;
987
988 switch (p) {
989 case _CK_MPU:
990 /* MPU sub system */
991 reg = readl(priv->base + RCC_MPCKSELR);
992 switch (reg & RCC_SELR_SRC_MASK) {
993 case RCC_MPCKSELR_HSI:
994 clock = stm32mp1_clk_get_fixed(priv, _HSI);
995 break;
996 case RCC_MPCKSELR_HSE:
997 clock = stm32mp1_clk_get_fixed(priv, _HSE);
998 break;
999 case RCC_MPCKSELR_PLL:
1000 case RCC_MPCKSELR_PLL_MPUDIV:
1001 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
1002 if ((reg & RCC_SELR_SRC_MASK) ==
1003 RCC_MPCKSELR_PLL_MPUDIV) {
1004 reg = readl(priv->base + RCC_MPCKDIVR);
1005 clock >>= stm32mp1_mpu_div[reg &
1006 RCC_MPUDIV_MASK];
1007 }
1008 break;
1009 }
1010 break;
1011 /* AXI sub system */
1012 case _ACLK:
1013 case _HCLK2:
1014 case _HCLK6:
1015 case _PCLK4:
1016 case _PCLK5:
1017 reg = readl(priv->base + RCC_ASSCKSELR);
1018 switch (reg & RCC_SELR_SRC_MASK) {
1019 case RCC_ASSCKSELR_HSI:
1020 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1021 break;
1022 case RCC_ASSCKSELR_HSE:
1023 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1024 break;
1025 case RCC_ASSCKSELR_PLL:
1026 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
1027 break;
1028 }
1029
1030 /* System clock divider */
1031 reg = readl(priv->base + RCC_AXIDIVR);
1032 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
1033
1034 switch (p) {
1035 case _PCLK4:
1036 reg = readl(priv->base + RCC_APB4DIVR);
1037 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1038 break;
1039 case _PCLK5:
1040 reg = readl(priv->base + RCC_APB5DIVR);
1041 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1042 break;
1043 default:
1044 break;
1045 }
1046 break;
1047 /* MCU sub system */
1048 case _CK_MCU:
1049 case _PCLK1:
1050 case _PCLK2:
1051 case _PCLK3:
1052 reg = readl(priv->base + RCC_MSSCKSELR);
1053 switch (reg & RCC_SELR_SRC_MASK) {
1054 case RCC_MSSCKSELR_HSI:
1055 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1056 break;
1057 case RCC_MSSCKSELR_HSE:
1058 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1059 break;
1060 case RCC_MSSCKSELR_CSI:
1061 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1062 break;
1063 case RCC_MSSCKSELR_PLL:
1064 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1065 break;
1066 }
1067
1068 /* MCU clock divider */
1069 reg = readl(priv->base + RCC_MCUDIVR);
1070 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1071
1072 switch (p) {
1073 case _PCLK1:
1074 reg = readl(priv->base + RCC_APB1DIVR);
1075 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1076 break;
1077 case _PCLK2:
1078 reg = readl(priv->base + RCC_APB2DIVR);
1079 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1080 break;
1081 case _PCLK3:
1082 reg = readl(priv->base + RCC_APB3DIVR);
1083 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1084 break;
1085 case _CK_MCU:
1086 default:
1087 break;
1088 }
1089 break;
1090 case _CK_PER:
1091 reg = readl(priv->base + RCC_CPERCKSELR);
1092 switch (reg & RCC_SELR_SRC_MASK) {
1093 case RCC_CPERCKSELR_HSI:
1094 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1095 break;
1096 case RCC_CPERCKSELR_HSE:
1097 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1098 break;
1099 case RCC_CPERCKSELR_CSI:
1100 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1101 break;
1102 }
1103 break;
1104 case _HSI:
1105 case _HSI_KER:
1106 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1107 break;
1108 case _CSI:
1109 case _CSI_KER:
1110 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1111 break;
1112 case _HSE:
1113 case _HSE_KER:
1114 case _HSE_KER_DIV2:
1115 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1116 if (p == _HSE_KER_DIV2)
1117 clock >>= 1;
1118 break;
1119 case _LSI:
1120 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1121 break;
1122 case _LSE:
1123 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1124 break;
1125 /* PLL */
1126 case _PLL1_P:
1127 case _PLL1_Q:
1128 case _PLL1_R:
1129 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1130 break;
1131 case _PLL2_P:
1132 case _PLL2_Q:
1133 case _PLL2_R:
1134 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1135 break;
1136 case _PLL3_P:
1137 case _PLL3_Q:
1138 case _PLL3_R:
1139 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1140 break;
1141 case _PLL4_P:
1142 case _PLL4_Q:
1143 case _PLL4_R:
1144 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1145 break;
1146 /* other */
1147 case _USB_PHY_48:
1148 clock = stm32mp1_clk_get_by_name("ck_usbo_48m");
1149 break;
1150 case _DSI_PHY:
1151 clock = stm32mp1_clk_get_by_name("ck_dsi_phy");
1152 break;
1153 default:
1154 break;
1155 }
1156
1157 log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
1158
1159 return clock;
1160 }
1161
stm32mp1_clk_enable(struct clk * clk)1162 static int stm32mp1_clk_enable(struct clk *clk)
1163 {
1164 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1165 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1166 int i = stm32mp1_clk_get_id(priv, clk->id);
1167
1168 if (i < 0)
1169 return i;
1170
1171 if (gate[i].set_clr)
1172 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1173 else
1174 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1175
1176 dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1177
1178 return 0;
1179 }
1180
stm32mp1_clk_disable(struct clk * clk)1181 static int stm32mp1_clk_disable(struct clk *clk)
1182 {
1183 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1184 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1185 int i = stm32mp1_clk_get_id(priv, clk->id);
1186
1187 if (i < 0)
1188 return i;
1189
1190 if (gate[i].set_clr)
1191 writel(BIT(gate[i].bit),
1192 priv->base + gate[i].offset
1193 + RCC_MP_ENCLRR_OFFSET);
1194 else
1195 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1196
1197 dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1198
1199 return 0;
1200 }
1201
stm32mp1_clk_get_rate(struct clk * clk)1202 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1203 {
1204 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1205 int p = stm32mp1_clk_get_parent(priv, clk->id);
1206 ulong rate;
1207
1208 if (p < 0)
1209 return 0;
1210
1211 rate = stm32mp1_clk_get(priv, p);
1212
1213 dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
1214 (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1215
1216 return rate;
1217 }
1218
1219 #ifdef STM32MP1_CLOCK_TREE_INIT
1220
stm32mp1_supports_opp(u32 opp_id,u32 cpu_type)1221 bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
1222 {
1223 unsigned int id;
1224
1225 switch (opp_id) {
1226 case 1:
1227 case 2:
1228 id = opp_id;
1229 break;
1230 default:
1231 id = 1; /* default value */
1232 break;
1233 }
1234
1235 switch (cpu_type) {
1236 case CPU_STM32MP157Fxx:
1237 case CPU_STM32MP157Dxx:
1238 case CPU_STM32MP153Fxx:
1239 case CPU_STM32MP153Dxx:
1240 case CPU_STM32MP151Fxx:
1241 case CPU_STM32MP151Dxx:
1242 return true;
1243 default:
1244 return id == 1;
1245 }
1246 }
1247
board_vddcore_init(u32 voltage_mv)1248 __weak void board_vddcore_init(u32 voltage_mv)
1249 {
1250 }
1251
1252 /*
1253 * gets OPP parameters (frequency in KHz and voltage in mV) from
1254 * an OPP table subnode. Platform HW support capabilities are also checked.
1255 * Returns 0 on success and a negative FDT error code on failure.
1256 */
stm32mp1_get_opp(u32 cpu_type,ofnode subnode,u32 * freq_khz,u32 * voltage_mv)1257 static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
1258 u32 *freq_khz, u32 *voltage_mv)
1259 {
1260 u32 opp_hw;
1261 u64 read_freq_64;
1262 u32 read_voltage_32;
1263
1264 *freq_khz = 0;
1265 *voltage_mv = 0;
1266
1267 opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
1268 if (opp_hw)
1269 if (!stm32mp1_supports_opp(opp_hw, cpu_type))
1270 return -FDT_ERR_BADVALUE;
1271
1272 read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
1273 1000ULL;
1274 read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
1275 1000U;
1276
1277 if (!read_voltage_32 || !read_freq_64)
1278 return -FDT_ERR_NOTFOUND;
1279
1280 /* Frequency value expressed in KHz must fit on 32 bits */
1281 if (read_freq_64 > U32_MAX)
1282 return -FDT_ERR_BADVALUE;
1283
1284 /* Millivolt value must fit on 16 bits */
1285 if (read_voltage_32 > U16_MAX)
1286 return -FDT_ERR_BADVALUE;
1287
1288 *freq_khz = (u32)read_freq_64;
1289 *voltage_mv = read_voltage_32;
1290
1291 return 0;
1292 }
1293
1294 /*
1295 * parses OPP table in DT and finds the parameters for the
1296 * highest frequency supported by the HW platform.
1297 * Returns 0 on success and a negative FDT error code on failure.
1298 */
stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv * priv,u64 * freq_hz)1299 int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
1300 {
1301 ofnode node, subnode;
1302 int ret;
1303 u32 freq = 0U, voltage = 0U;
1304 u32 cpu_type = get_cpu_type();
1305
1306 node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
1307 if (!ofnode_valid(node))
1308 return -FDT_ERR_NOTFOUND;
1309
1310 ofnode_for_each_subnode(subnode, node) {
1311 unsigned int read_freq;
1312 unsigned int read_voltage;
1313
1314 ret = stm32mp1_get_opp(cpu_type, subnode,
1315 &read_freq, &read_voltage);
1316 if (ret)
1317 continue;
1318
1319 if (read_freq > freq) {
1320 freq = read_freq;
1321 voltage = read_voltage;
1322 }
1323 }
1324
1325 if (!freq || !voltage)
1326 return -FDT_ERR_NOTFOUND;
1327
1328 *freq_hz = (u64)1000U * freq;
1329 board_vddcore_init(voltage);
1330
1331 return 0;
1332 }
1333
stm32mp1_pll1_opp(struct stm32mp1_clk_priv * priv,int clksrc,u32 * pllcfg,u32 * fracv)1334 static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
1335 u32 *pllcfg, u32 *fracv)
1336 {
1337 u32 post_divm;
1338 u32 input_freq;
1339 u64 output_freq;
1340 u64 freq;
1341 u64 vco;
1342 u32 divm, divn, divp, frac;
1343 int i, ret;
1344 u32 diff;
1345 u32 best_diff = U32_MAX;
1346
1347 /* PLL1 is 1600 */
1348 const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
1349 const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
1350 const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
1351
1352 ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
1353 if (ret) {
1354 log_debug("PLL1 OPP configuration not found (%d).\n", ret);
1355 return ret;
1356 }
1357
1358 switch (clksrc) {
1359 case CLK_PLL12_HSI:
1360 input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
1361 break;
1362 case CLK_PLL12_HSE:
1363 input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
1364 break;
1365 default:
1366 return -EINTR;
1367 }
1368
1369 /* Following parameters have always the same value */
1370 pllcfg[PLLCFG_Q] = 0;
1371 pllcfg[PLLCFG_R] = 0;
1372 pllcfg[PLLCFG_O] = PQR(1, 0, 0);
1373
1374 for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
1375 post_divm = (u32)(input_freq / (divm + 1));
1376 if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
1377 continue;
1378
1379 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1380 freq = output_freq * (divm + 1) * (divp + 1);
1381 divn = (u32)((freq / input_freq) - 1);
1382 if (divn < DIVN_MIN || divn > DIVN_MAX)
1383 continue;
1384
1385 frac = (u32)(((freq * FRAC_MAX) / input_freq) -
1386 ((divn + 1) * FRAC_MAX));
1387 /* 2 loops to refine the fractional part */
1388 for (i = 2; i != 0; i--) {
1389 if (frac > FRAC_MAX)
1390 break;
1391
1392 vco = (post_divm * (divn + 1)) +
1393 ((post_divm * (u64)frac) /
1394 FRAC_MAX);
1395 if (vco < (PLL1600_VCO_MIN / 2) ||
1396 vco > (PLL1600_VCO_MAX / 2)) {
1397 frac++;
1398 continue;
1399 }
1400 freq = vco / (divp + 1);
1401 if (output_freq < freq)
1402 diff = (u32)(freq - output_freq);
1403 else
1404 diff = (u32)(output_freq - freq);
1405 if (diff < best_diff) {
1406 pllcfg[PLLCFG_M] = divm;
1407 pllcfg[PLLCFG_N] = divn;
1408 pllcfg[PLLCFG_P] = divp;
1409 *fracv = frac;
1410
1411 if (diff == 0)
1412 return 0;
1413
1414 best_diff = diff;
1415 }
1416 frac++;
1417 }
1418 }
1419 }
1420
1421 if (best_diff == U32_MAX)
1422 return -1;
1423
1424 return 0;
1425 }
1426
stm32mp1_ls_osc_set(int enable,fdt_addr_t rcc,u32 offset,u32 mask_on)1427 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1428 u32 mask_on)
1429 {
1430 u32 address = rcc + offset;
1431
1432 if (enable)
1433 setbits_le32(address, mask_on);
1434 else
1435 clrbits_le32(address, mask_on);
1436 }
1437
stm32mp1_hs_ocs_set(int enable,fdt_addr_t rcc,u32 mask_on)1438 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1439 {
1440 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1441 }
1442
stm32mp1_osc_wait(int enable,fdt_addr_t rcc,u32 offset,u32 mask_rdy)1443 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1444 u32 mask_rdy)
1445 {
1446 u32 mask_test = 0;
1447 u32 address = rcc + offset;
1448 u32 val;
1449 int ret;
1450
1451 if (enable)
1452 mask_test = mask_rdy;
1453
1454 ret = readl_poll_timeout(address, val,
1455 (val & mask_rdy) == mask_test,
1456 TIMEOUT_1S);
1457
1458 if (ret)
1459 log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1460 mask_rdy, address, enable, readl(address));
1461
1462 return ret;
1463 }
1464
stm32mp1_lse_enable(fdt_addr_t rcc,int bypass,int digbyp,u32 lsedrv)1465 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1466 u32 lsedrv)
1467 {
1468 u32 value;
1469
1470 if (digbyp)
1471 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1472
1473 if (bypass || digbyp)
1474 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1475
1476 /*
1477 * warning: not recommended to switch directly from "high drive"
1478 * to "medium low drive", and vice-versa.
1479 */
1480 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1481 >> RCC_BDCR_LSEDRV_SHIFT;
1482
1483 while (value != lsedrv) {
1484 if (value > lsedrv)
1485 value--;
1486 else
1487 value++;
1488
1489 clrsetbits_le32(rcc + RCC_BDCR,
1490 RCC_BDCR_LSEDRV_MASK,
1491 value << RCC_BDCR_LSEDRV_SHIFT);
1492 }
1493
1494 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1495 }
1496
stm32mp1_lse_wait(fdt_addr_t rcc)1497 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1498 {
1499 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1500 }
1501
stm32mp1_lsi_set(fdt_addr_t rcc,int enable)1502 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1503 {
1504 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1505 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1506 }
1507
stm32mp1_hse_enable(fdt_addr_t rcc,int bypass,int digbyp,int css)1508 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1509 {
1510 if (digbyp)
1511 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1512 if (bypass || digbyp)
1513 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1514
1515 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1516 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1517
1518 if (css)
1519 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1520 }
1521
stm32mp1_csi_set(fdt_addr_t rcc,int enable)1522 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1523 {
1524 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1525 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1526 }
1527
stm32mp1_hsi_set(fdt_addr_t rcc,int enable)1528 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1529 {
1530 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1531 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1532 }
1533
stm32mp1_set_hsidiv(fdt_addr_t rcc,u8 hsidiv)1534 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1535 {
1536 u32 address = rcc + RCC_OCRDYR;
1537 u32 val;
1538 int ret;
1539
1540 clrsetbits_le32(rcc + RCC_HSICFGR,
1541 RCC_HSICFGR_HSIDIV_MASK,
1542 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1543
1544 ret = readl_poll_timeout(address, val,
1545 val & RCC_OCRDYR_HSIDIVRDY,
1546 TIMEOUT_200MS);
1547 if (ret)
1548 log_err("HSIDIV failed @ 0x%x: 0x%x\n",
1549 address, readl(address));
1550
1551 return ret;
1552 }
1553
stm32mp1_hsidiv(fdt_addr_t rcc,ulong hsifreq)1554 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1555 {
1556 u8 hsidiv;
1557 u32 hsidivfreq = MAX_HSI_HZ;
1558
1559 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1560 hsidivfreq = hsidivfreq / 2)
1561 if (hsidivfreq == hsifreq)
1562 break;
1563
1564 if (hsidiv == 4) {
1565 log_err("hsi frequency invalid");
1566 return -1;
1567 }
1568
1569 if (hsidiv > 0)
1570 return stm32mp1_set_hsidiv(rcc, hsidiv);
1571
1572 return 0;
1573 }
1574
pll_start(struct stm32mp1_clk_priv * priv,int pll_id)1575 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1576 {
1577 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1578
1579 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1580 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1581 RCC_PLLNCR_DIVREN,
1582 RCC_PLLNCR_PLLON);
1583 }
1584
pll_output(struct stm32mp1_clk_priv * priv,int pll_id,int output)1585 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1586 {
1587 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1588 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1589 u32 val;
1590 int ret;
1591
1592 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1593 TIMEOUT_200MS);
1594
1595 if (ret) {
1596 log_err("PLL%d start failed @ 0x%x: 0x%x\n",
1597 pll_id, pllxcr, readl(pllxcr));
1598 return ret;
1599 }
1600
1601 /* start the requested output */
1602 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1603
1604 return 0;
1605 }
1606
pll_stop(struct stm32mp1_clk_priv * priv,int pll_id)1607 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1608 {
1609 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1610 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1611 u32 val;
1612
1613 /* stop all output */
1614 clrbits_le32(pllxcr,
1615 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1616
1617 /* stop PLL */
1618 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1619
1620 /* wait PLL stopped */
1621 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1622 TIMEOUT_200MS);
1623 }
1624
pll_config_output(struct stm32mp1_clk_priv * priv,int pll_id,u32 * pllcfg)1625 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1626 int pll_id, u32 *pllcfg)
1627 {
1628 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1629 fdt_addr_t rcc = priv->base;
1630 u32 value;
1631
1632 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1633 & RCC_PLLNCFGR2_DIVP_MASK;
1634 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1635 & RCC_PLLNCFGR2_DIVQ_MASK;
1636 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1637 & RCC_PLLNCFGR2_DIVR_MASK;
1638 writel(value, rcc + pll[pll_id].pllxcfgr2);
1639 }
1640
pll_config(struct stm32mp1_clk_priv * priv,int pll_id,u32 * pllcfg,u32 fracv)1641 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1642 u32 *pllcfg, u32 fracv)
1643 {
1644 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1645 fdt_addr_t rcc = priv->base;
1646 enum stm32mp1_plltype type = pll[pll_id].plltype;
1647 int src;
1648 ulong refclk;
1649 u8 ifrge = 0;
1650 u32 value;
1651
1652 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1653
1654 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1655 (pllcfg[PLLCFG_M] + 1);
1656
1657 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1658 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1659 log_err("invalid refclk = %x\n", (u32)refclk);
1660 return -EINVAL;
1661 }
1662 if (type == PLL_800 && refclk >= 8000000)
1663 ifrge = 1;
1664
1665 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1666 & RCC_PLLNCFGR1_DIVN_MASK;
1667 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1668 & RCC_PLLNCFGR1_DIVM_MASK;
1669 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1670 & RCC_PLLNCFGR1_IFRGE_MASK;
1671 writel(value, rcc + pll[pll_id].pllxcfgr1);
1672
1673 /* fractional configuration: load sigma-delta modulator (SDM) */
1674
1675 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1676 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1677 rcc + pll[pll_id].pllxfracr);
1678
1679 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1680 setbits_le32(rcc + pll[pll_id].pllxfracr,
1681 RCC_PLLNFRACR_FRACLE);
1682
1683 pll_config_output(priv, pll_id, pllcfg);
1684
1685 return 0;
1686 }
1687
pll_csg(struct stm32mp1_clk_priv * priv,int pll_id,u32 * csg)1688 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1689 {
1690 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1691 u32 pllxcsg;
1692
1693 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1694 RCC_PLLNCSGR_MOD_PER_MASK) |
1695 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1696 RCC_PLLNCSGR_INC_STEP_MASK) |
1697 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1698 RCC_PLLNCSGR_SSCG_MODE_MASK);
1699
1700 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1701
1702 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1703 }
1704
pll_set_rate(struct udevice * dev,int pll_id,int div_id,unsigned long clk_rate)1705 static __maybe_unused int pll_set_rate(struct udevice *dev,
1706 int pll_id,
1707 int div_id,
1708 unsigned long clk_rate)
1709 {
1710 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1711 unsigned int pllcfg[PLLCFG_NB];
1712 ofnode plloff;
1713 char name[12];
1714 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1715 enum stm32mp1_plltype type = pll[pll_id].plltype;
1716 int divm, divn, divy;
1717 int ret;
1718 ulong fck_ref;
1719 u32 fracv;
1720 u64 value;
1721
1722 if (div_id > _DIV_NB)
1723 return -EINVAL;
1724
1725 sprintf(name, "st,pll@%d", pll_id);
1726 plloff = dev_read_subnode(dev, name);
1727 if (!ofnode_valid(plloff))
1728 return -FDT_ERR_NOTFOUND;
1729
1730 ret = ofnode_read_u32_array(plloff, "cfg",
1731 pllcfg, PLLCFG_NB);
1732 if (ret < 0)
1733 return -FDT_ERR_NOTFOUND;
1734
1735 fck_ref = pll_get_fref_ck(priv, pll_id);
1736
1737 divm = pllcfg[PLLCFG_M];
1738 /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1739 divy = pllcfg[PLLCFG_P + div_id];
1740
1741 /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1742 * So same final result than PLL2 et 4
1743 * with FRACV
1744 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1745 * / (DIVy + 1) * (DIVM + 1)
1746 * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1747 * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1748 */
1749 value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1750 value = lldiv(value, fck_ref);
1751
1752 divn = (value >> 13) - 1;
1753 if (divn < DIVN_MIN ||
1754 divn > stm32mp1_pll[type].divn_max) {
1755 dev_err(dev, "divn invalid = %d", divn);
1756 return -EINVAL;
1757 }
1758 fracv = value - ((divn + 1) << 13);
1759 pllcfg[PLLCFG_N] = divn;
1760
1761 /* reconfigure PLL */
1762 pll_stop(priv, pll_id);
1763 pll_config(priv, pll_id, pllcfg, fracv);
1764 pll_start(priv, pll_id);
1765 pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1766
1767 return 0;
1768 }
1769
set_clksrc(struct stm32mp1_clk_priv * priv,unsigned int clksrc)1770 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1771 {
1772 u32 address = priv->base + (clksrc >> 4);
1773 u32 val;
1774 int ret;
1775
1776 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1777 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1778 TIMEOUT_200MS);
1779 if (ret)
1780 log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1781 clksrc, address, readl(address));
1782
1783 return ret;
1784 }
1785
stgen_config(struct stm32mp1_clk_priv * priv)1786 static void stgen_config(struct stm32mp1_clk_priv *priv)
1787 {
1788 int p;
1789 u32 stgenc, cntfid0;
1790 ulong rate;
1791
1792 stgenc = STM32_STGEN_BASE;
1793 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1794 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1795 rate = stm32mp1_clk_get(priv, p);
1796
1797 if (cntfid0 != rate) {
1798 u64 counter;
1799
1800 log_debug("System Generic Counter (STGEN) update\n");
1801 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1802 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1803 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1804 counter = lldiv(counter * (u64)rate, cntfid0);
1805 writel((u32)counter, stgenc + STGENC_CNTCVL);
1806 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1807 writel(rate, stgenc + STGENC_CNTFID0);
1808 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1809
1810 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1811
1812 /* need to update gd->arch.timer_rate_hz with new frequency */
1813 timer_init();
1814 }
1815 }
1816
set_clkdiv(unsigned int clkdiv,u32 address)1817 static int set_clkdiv(unsigned int clkdiv, u32 address)
1818 {
1819 u32 val;
1820 int ret;
1821
1822 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1823 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1824 TIMEOUT_200MS);
1825 if (ret)
1826 log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1827 clkdiv, address, readl(address));
1828
1829 return ret;
1830 }
1831
stm32mp1_mco_csg(struct stm32mp1_clk_priv * priv,u32 clksrc,u32 clkdiv)1832 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1833 u32 clksrc, u32 clkdiv)
1834 {
1835 u32 address = priv->base + (clksrc >> 4);
1836
1837 /*
1838 * binding clksrc : bit15-4 offset
1839 * bit3: disable
1840 * bit2-0: MCOSEL[2:0]
1841 */
1842 if (clksrc & 0x8) {
1843 clrbits_le32(address, RCC_MCOCFG_MCOON);
1844 } else {
1845 clrsetbits_le32(address,
1846 RCC_MCOCFG_MCOSRC_MASK,
1847 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1848 clrsetbits_le32(address,
1849 RCC_MCOCFG_MCODIV_MASK,
1850 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1851 setbits_le32(address, RCC_MCOCFG_MCOON);
1852 }
1853 }
1854
set_rtcsrc(struct stm32mp1_clk_priv * priv,unsigned int clksrc,int lse_css)1855 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1856 unsigned int clksrc,
1857 int lse_css)
1858 {
1859 u32 address = priv->base + RCC_BDCR;
1860
1861 if (readl(address) & RCC_BDCR_RTCCKEN)
1862 goto skip_rtc;
1863
1864 if (clksrc == CLK_RTC_DISABLED)
1865 goto skip_rtc;
1866
1867 clrsetbits_le32(address,
1868 RCC_BDCR_RTCSRC_MASK,
1869 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1870
1871 setbits_le32(address, RCC_BDCR_RTCCKEN);
1872
1873 skip_rtc:
1874 if (lse_css)
1875 setbits_le32(address, RCC_BDCR_LSECSSON);
1876 }
1877
pkcs_config(struct stm32mp1_clk_priv * priv,u32 pkcs)1878 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1879 {
1880 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1881 u32 value = pkcs & 0xF;
1882 u32 mask = 0xF;
1883
1884 if (pkcs & BIT(31)) {
1885 mask <<= 4;
1886 value <<= 4;
1887 }
1888 clrsetbits_le32(address, mask, value);
1889 }
1890
stm32mp1_clktree(struct udevice * dev)1891 static int stm32mp1_clktree(struct udevice *dev)
1892 {
1893 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1894 fdt_addr_t rcc = priv->base;
1895 unsigned int clksrc[CLKSRC_NB];
1896 unsigned int clkdiv[CLKDIV_NB];
1897 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1898 unsigned int pllfracv[_PLL_NB];
1899 unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
1900 bool pllcfg_valid[_PLL_NB];
1901 bool pllcsg_set[_PLL_NB];
1902 int ret;
1903 int i, len;
1904 int lse_css = 0;
1905 const u32 *pkcs_cell;
1906
1907 /* check mandatory field */
1908 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1909 if (ret < 0) {
1910 dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
1911 return -FDT_ERR_NOTFOUND;
1912 }
1913
1914 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1915 if (ret < 0) {
1916 dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
1917 return -FDT_ERR_NOTFOUND;
1918 }
1919
1920 /* check mandatory field in each pll */
1921 for (i = 0; i < _PLL_NB; i++) {
1922 char name[12];
1923 ofnode node;
1924
1925 sprintf(name, "st,pll@%d", i);
1926 node = dev_read_subnode(dev, name);
1927 pllcfg_valid[i] = ofnode_valid(node);
1928 pllcsg_set[i] = false;
1929 if (pllcfg_valid[i]) {
1930 dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
1931 ret = ofnode_read_u32_array(node, "cfg",
1932 pllcfg[i], PLLCFG_NB);
1933 if (ret < 0) {
1934 dev_dbg(dev, "field cfg invalid: error %d\n", ret);
1935 return -FDT_ERR_NOTFOUND;
1936 }
1937 pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
1938
1939 ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
1940 PLLCSG_NB);
1941 if (!ret) {
1942 pllcsg_set[i] = true;
1943 } else if (ret != -FDT_ERR_NOTFOUND) {
1944 dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
1945 i, ret);
1946 return ret;
1947 }
1948 } else if (i == _PLL1) {
1949 /* use OPP for PLL1 for A7 CPU */
1950 dev_dbg(dev, "DT for PLL %d with OPP\n", i);
1951 ret = stm32mp1_pll1_opp(priv,
1952 clksrc[CLKSRC_PLL12],
1953 pllcfg[i],
1954 &pllfracv[i]);
1955 if (ret) {
1956 dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
1957 return ret;
1958 }
1959 pllcfg_valid[i] = true;
1960 }
1961 }
1962
1963 dev_dbg(dev, "configuration MCO\n");
1964 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1965 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1966
1967 dev_dbg(dev, "switch ON osillator\n");
1968 /*
1969 * switch ON oscillator found in device-tree,
1970 * HSI already ON after bootrom
1971 */
1972 if (clk_valid(&priv->osc_clk[_LSI]))
1973 stm32mp1_lsi_set(rcc, 1);
1974
1975 if (clk_valid(&priv->osc_clk[_LSE])) {
1976 int bypass, digbyp;
1977 u32 lsedrv;
1978 struct udevice *dev = priv->osc_clk[_LSE].dev;
1979
1980 bypass = dev_read_bool(dev, "st,bypass");
1981 digbyp = dev_read_bool(dev, "st,digbypass");
1982 lse_css = dev_read_bool(dev, "st,css");
1983 lsedrv = dev_read_u32_default(dev, "st,drive",
1984 LSEDRV_MEDIUM_HIGH);
1985
1986 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1987 }
1988
1989 if (clk_valid(&priv->osc_clk[_HSE])) {
1990 int bypass, digbyp, css;
1991 struct udevice *dev = priv->osc_clk[_HSE].dev;
1992
1993 bypass = dev_read_bool(dev, "st,bypass");
1994 digbyp = dev_read_bool(dev, "st,digbypass");
1995 css = dev_read_bool(dev, "st,css");
1996
1997 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1998 }
1999 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
2000 * => switch on CSI even if node is not present in device tree
2001 */
2002 stm32mp1_csi_set(rcc, 1);
2003
2004 /* come back to HSI */
2005 dev_dbg(dev, "come back to HSI\n");
2006 set_clksrc(priv, CLK_MPU_HSI);
2007 set_clksrc(priv, CLK_AXI_HSI);
2008 set_clksrc(priv, CLK_MCU_HSI);
2009
2010 dev_dbg(dev, "pll stop\n");
2011 for (i = 0; i < _PLL_NB; i++)
2012 pll_stop(priv, i);
2013
2014 /* configure HSIDIV */
2015 dev_dbg(dev, "configure HSIDIV\n");
2016 if (clk_valid(&priv->osc_clk[_HSI])) {
2017 stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI]));
2018 stgen_config(priv);
2019 }
2020
2021 /* select DIV */
2022 dev_dbg(dev, "select DIV\n");
2023 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
2024 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
2025 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
2026 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
2027 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
2028 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
2029 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
2030 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
2031 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
2032
2033 /* no ready bit for RTC */
2034 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
2035
2036 /* configure PLLs source */
2037 dev_dbg(dev, "configure PLLs source\n");
2038 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
2039 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
2040 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
2041
2042 /* configure and start PLLs */
2043 dev_dbg(dev, "configure PLLs\n");
2044 for (i = 0; i < _PLL_NB; i++) {
2045 if (!pllcfg_valid[i])
2046 continue;
2047 dev_dbg(dev, "configure PLL %d\n", i);
2048 pll_config(priv, i, pllcfg[i], pllfracv[i]);
2049 if (pllcsg_set[i])
2050 pll_csg(priv, i, pllcsg[i]);
2051 pll_start(priv, i);
2052 }
2053
2054 /* wait and start PLLs ouptut when ready */
2055 for (i = 0; i < _PLL_NB; i++) {
2056 if (!pllcfg_valid[i])
2057 continue;
2058 dev_dbg(dev, "output PLL %d\n", i);
2059 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
2060 }
2061
2062 /* wait LSE ready before to use it */
2063 if (clk_valid(&priv->osc_clk[_LSE]))
2064 stm32mp1_lse_wait(rcc);
2065
2066 /* configure with expected clock source */
2067 dev_dbg(dev, "CLKSRC\n");
2068 set_clksrc(priv, clksrc[CLKSRC_MPU]);
2069 set_clksrc(priv, clksrc[CLKSRC_AXI]);
2070 set_clksrc(priv, clksrc[CLKSRC_MCU]);
2071 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
2072
2073 /* configure PKCK */
2074 dev_dbg(dev, "PKCK\n");
2075 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
2076 if (pkcs_cell) {
2077 bool ckper_disabled = false;
2078
2079 for (i = 0; i < len / sizeof(u32); i++) {
2080 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
2081
2082 if (pkcs == CLK_CKPER_DISABLED) {
2083 ckper_disabled = true;
2084 continue;
2085 }
2086 pkcs_config(priv, pkcs);
2087 }
2088 /* CKPER is source for some peripheral clock
2089 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2090 * only if previous clock is still ON
2091 * => deactivated CKPER only after switching clock
2092 */
2093 if (ckper_disabled)
2094 pkcs_config(priv, CLK_CKPER_DISABLED);
2095 }
2096
2097 /* STGEN clock source can change with CLK_STGEN_XXX */
2098 stgen_config(priv);
2099
2100 dev_dbg(dev, "oscillator off\n");
2101 /* switch OFF HSI if not found in device-tree */
2102 if (!clk_valid(&priv->osc_clk[_HSI]))
2103 stm32mp1_hsi_set(rcc, 0);
2104
2105 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2106 clrsetbits_le32(priv->base + RCC_DDRITFCR,
2107 RCC_DDRITFCR_DDRCKMOD_MASK,
2108 RCC_DDRITFCR_DDRCKMOD_SSR <<
2109 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2110
2111 return 0;
2112 }
2113 #endif /* STM32MP1_CLOCK_TREE_INIT */
2114
pll_set_output_rate(struct udevice * dev,int pll_id,int div_id,unsigned long clk_rate)2115 static int pll_set_output_rate(struct udevice *dev,
2116 int pll_id,
2117 int div_id,
2118 unsigned long clk_rate)
2119 {
2120 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2121 const struct stm32mp1_clk_pll *pll = priv->data->pll;
2122 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
2123 int div;
2124 ulong fvco;
2125
2126 if (div_id > _DIV_NB)
2127 return -EINVAL;
2128
2129 fvco = pll_get_fvco(priv, pll_id);
2130
2131 if (fvco <= clk_rate)
2132 div = 1;
2133 else
2134 div = DIV_ROUND_UP(fvco, clk_rate);
2135
2136 if (div > 128)
2137 div = 128;
2138
2139 /* stop the requested output */
2140 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2141 /* change divider */
2142 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
2143 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
2144 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
2145 /* start the requested output */
2146 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2147
2148 return 0;
2149 }
2150
stm32mp1_clk_set_rate(struct clk * clk,unsigned long clk_rate)2151 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
2152 {
2153 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
2154 int p;
2155
2156 switch (clk->id) {
2157 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
2158 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2159 case DDRPHYC:
2160 break;
2161 #endif
2162 case LTDC_PX:
2163 case DSI_PX:
2164 break;
2165 default:
2166 dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
2167 return -EINVAL;
2168 }
2169
2170 p = stm32mp1_clk_get_parent(priv, clk->id);
2171 dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
2172 if (p < 0)
2173 return -EINVAL;
2174
2175 switch (p) {
2176 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
2177 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2178 case _PLL2_R: /* DDRPHYC */
2179 {
2180 /* only for change DDR clock in interactive mode */
2181 ulong result;
2182
2183 set_clksrc(priv, CLK_AXI_HSI);
2184 result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
2185 set_clksrc(priv, CLK_AXI_PLL2P);
2186 return result;
2187 }
2188 #endif
2189
2190 case _PLL4_Q:
2191 /* for LTDC_PX and DSI_PX case */
2192 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
2193 }
2194
2195 return -EINVAL;
2196 }
2197
stm32mp1_osc_init(struct udevice * dev)2198 static void stm32mp1_osc_init(struct udevice *dev)
2199 {
2200 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2201 int i;
2202 const char *name[NB_OSC] = {
2203 [_LSI] = "lsi",
2204 [_LSE] = "lse",
2205 [_HSI] = "hsi",
2206 [_HSE] = "hse",
2207 [_CSI] = "csi",
2208 [_I2S_CKIN] = "i2s_ckin",
2209 };
2210
2211 for (i = 0; i < NB_OSC; i++) {
2212 if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
2213 dev_dbg(dev, "No source clock \"%s\"\n", name[i]);
2214 else
2215 dev_dbg(dev, "%s clock rate: %luHz\n",
2216 name[i], clk_get_rate(&priv->osc_clk[i]));
2217 }
2218 }
2219
stm32mp1_clk_dump(struct stm32mp1_clk_priv * priv)2220 static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
2221 {
2222 char buf[32];
2223 int i, s, p;
2224
2225 printf("Clocks:\n");
2226 for (i = 0; i < _PARENT_NB; i++) {
2227 printf("- %s : %s MHz\n",
2228 stm32mp1_clk_parent_name[i],
2229 strmhz(buf, stm32mp1_clk_get(priv, i)));
2230 }
2231 printf("Source Clocks:\n");
2232 for (i = 0; i < _PARENT_SEL_NB; i++) {
2233 p = (readl(priv->base + priv->data->sel[i].offset) >>
2234 priv->data->sel[i].src) & priv->data->sel[i].msk;
2235 if (p < priv->data->sel[i].nb_parent) {
2236 s = priv->data->sel[i].parent[p];
2237 printf("- %s(%d) => parent %s(%d)\n",
2238 stm32mp1_clk_parent_sel_name[i], i,
2239 stm32mp1_clk_parent_name[s], s);
2240 } else {
2241 printf("- %s(%d) => parent index %d is invalid\n",
2242 stm32mp1_clk_parent_sel_name[i], i, p);
2243 }
2244 }
2245 }
2246
2247 #ifdef CONFIG_CMD_CLK
soc_clk_dump(void)2248 int soc_clk_dump(void)
2249 {
2250 struct udevice *dev;
2251 struct stm32mp1_clk_priv *priv;
2252 int ret;
2253
2254 ret = uclass_get_device_by_driver(UCLASS_CLK,
2255 DM_DRIVER_GET(stm32mp1_clock),
2256 &dev);
2257 if (ret)
2258 return ret;
2259
2260 priv = dev_get_priv(dev);
2261
2262 stm32mp1_clk_dump(priv);
2263
2264 return 0;
2265 }
2266 #endif
2267
stm32mp1_clk_probe(struct udevice * dev)2268 static int stm32mp1_clk_probe(struct udevice *dev)
2269 {
2270 int result = 0;
2271 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2272
2273 priv->base = dev_read_addr(dev->parent);
2274 if (priv->base == FDT_ADDR_T_NONE)
2275 return -EINVAL;
2276
2277 priv->data = (void *)&stm32mp1_data;
2278
2279 if (!priv->data->gate || !priv->data->sel ||
2280 !priv->data->pll)
2281 return -EINVAL;
2282
2283 stm32mp1_osc_init(dev);
2284
2285 #ifdef STM32MP1_CLOCK_TREE_INIT
2286 /* clock tree init is done only one time, before relocation */
2287 if (!(gd->flags & GD_FLG_RELOC))
2288 result = stm32mp1_clktree(dev);
2289 if (result)
2290 dev_err(dev, "clock tree initialization failed (%d)\n", result);
2291 #endif
2292
2293 #ifndef CONFIG_SPL_BUILD
2294 #if defined(VERBOSE_DEBUG)
2295 /* display debug information for probe after relocation */
2296 if (gd->flags & GD_FLG_RELOC)
2297 stm32mp1_clk_dump(priv);
2298 #endif
2299
2300 gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2301 gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2302 /* DDRPHYC father */
2303 gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2304 #if defined(CONFIG_DISPLAY_CPUINFO)
2305 if (gd->flags & GD_FLG_RELOC) {
2306 char buf[32];
2307
2308 log_info("Clocks:\n");
2309 log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2310 log_info("- MCU : %s MHz\n",
2311 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2312 log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2313 log_info("- PER : %s MHz\n",
2314 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2315 log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2316 }
2317 #endif /* CONFIG_DISPLAY_CPUINFO */
2318 #endif
2319
2320 return result;
2321 }
2322
2323 static const struct clk_ops stm32mp1_clk_ops = {
2324 .enable = stm32mp1_clk_enable,
2325 .disable = stm32mp1_clk_disable,
2326 .get_rate = stm32mp1_clk_get_rate,
2327 .set_rate = stm32mp1_clk_set_rate,
2328 };
2329
2330 U_BOOT_DRIVER(stm32mp1_clock) = {
2331 .name = "stm32mp1_clk",
2332 .id = UCLASS_CLK,
2333 .ops = &stm32mp1_clk_ops,
2334 .priv_auto = sizeof(struct stm32mp1_clk_priv),
2335 .probe = stm32mp1_clk_probe,
2336 };
2337