1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2 /*
3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_CLK
8
9 #include <clk-uclass.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <asm/io.h>
14 #include <dt-bindings/clock/stm32mp13-clks.h>
15 #include <linux/clk-provider.h>
16
17 #include "clk-stm32-core.h"
18 #include "stm32mp13_rcc.h"
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 static const char * const adc12_src[] = {
23 "pll4_r", "ck_per", "pll3_q"
24 };
25
26 static const char * const dcmipp_src[] = {
27 "ck_axi", "pll2_q", "pll4_p", "ck_per",
28 };
29
30 static const char * const eth12_src[] = {
31 "pll4_p", "pll3_q"
32 };
33
34 static const char * const fdcan_src[] = {
35 "ck_hse", "pll3_q", "pll4_q", "pll4_r"
36 };
37
38 static const char * const fmc_src[] = {
39 "ck_axi", "pll3_r", "pll4_p", "ck_per"
40 };
41
42 static const char * const i2c12_src[] = {
43 "pclk1", "pll4_r", "ck_hsi", "ck_csi"
44 };
45
46 static const char * const i2c345_src[] = {
47 "pclk6", "pll4_r", "ck_hsi", "ck_csi"
48 };
49
50 static const char * const lptim1_src[] = {
51 "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
52 };
53
54 static const char * const lptim23_src[] = {
55 "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
56 };
57
58 static const char * const lptim45_src[] = {
59 "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
60 };
61
62 static const char * const mco1_src[] = {
63 "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
64 };
65
66 static const char * const mco2_src[] = {
67 "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
68 };
69
70 static const char * const qspi_src[] = {
71 "ck_axi", "pll3_r", "pll4_p", "ck_per"
72 };
73
74 static const char * const rng1_src[] = {
75 "ck_csi", "pll4_r", "reserved", "ck_lsi"
76 };
77
78 static const char * const saes_src[] = {
79 "ck_axi", "ck_per", "pll4_r", "ck_lsi"
80 };
81
82 static const char * const sai1_src[] = {
83 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
84 };
85
86 static const char * const sai2_src[] = {
87 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
88 };
89
90 static const char * const sdmmc12_src[] = {
91 "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
92 };
93
94 static const char * const spdif_src[] = {
95 "pll4_p", "pll3_q", "ck_hsi"
96 };
97
98 static const char * const spi123_src[] = {
99 "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
100 };
101
102 static const char * const spi4_src[] = {
103 "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin"
104 };
105
106 static const char * const spi5_src[] = {
107 "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
108 };
109
110 static const char * const stgen_src[] = {
111 "ck_hsi", "ck_hse"
112 };
113
114 static const char * const usart12_src[] = {
115 "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
116 };
117
118 static const char * const usart34578_src[] = {
119 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
120 };
121
122 static const char * const usart6_src[] = {
123 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
124 };
125
126 static const char * const usbo_src[] = {
127 "pll4_r", "ck_usbo_48m"
128 };
129
130 static const char * const usbphy_src[] = {
131 "ck_hse", "pll4_r", "clk-hse-div2"
132 };
133
134 enum enum_mux_cfg {
135 MUX_I2C12,
136 MUX_LPTIM45,
137 MUX_SPI23,
138 MUX_UART35,
139 MUX_UART78,
140 MUX_ADC1,
141 MUX_ADC2,
142 MUX_DCMIPP,
143 MUX_ETH1,
144 MUX_ETH2,
145 MUX_FDCAN,
146 MUX_FMC,
147 MUX_I2C3,
148 MUX_I2C4,
149 MUX_I2C5,
150 MUX_LPTIM1,
151 MUX_LPTIM2,
152 MUX_LPTIM3,
153 MUX_QSPI,
154 MUX_RNG1,
155 MUX_SAES,
156 MUX_SAI1,
157 MUX_SAI2,
158 MUX_SDMMC1,
159 MUX_SDMMC2,
160 MUX_SPDIF,
161 MUX_SPI1,
162 MUX_SPI4,
163 MUX_SPI5,
164 MUX_STGEN,
165 MUX_UART1,
166 MUX_UART2,
167 MUX_UART4,
168 MUX_UART6,
169 MUX_USBO,
170 MUX_USBPHY,
171 MUX_MCO1,
172 MUX_MCO2
173 };
174
175 #define MUX_CFG(id, src, _offset, _shift, _witdh) \
176 [id] = { \
177 .num_parents = ARRAY_SIZE(src), \
178 .parent_names = (src), \
179 .reg_off = (_offset), \
180 .shift = (_shift), \
181 .width = (_witdh), \
182 }
183
184 static const struct stm32_mux_cfg stm32mp13_muxes[] = {
185 MUX_CFG(MUX_I2C12, i2c12_src, RCC_I2C12CKSELR, 0, 3),
186 MUX_CFG(MUX_LPTIM45, lptim45_src, RCC_LPTIM45CKSELR, 0, 3),
187 MUX_CFG(MUX_SPI23, spi123_src, RCC_SPI2S23CKSELR, 0, 3),
188 MUX_CFG(MUX_UART35, usart34578_src, RCC_UART35CKSELR, 0, 3),
189 MUX_CFG(MUX_UART78, usart34578_src, RCC_UART78CKSELR, 0, 3),
190 MUX_CFG(MUX_ADC1, adc12_src, RCC_ADC12CKSELR, 0, 2),
191 MUX_CFG(MUX_ADC2, adc12_src, RCC_ADC12CKSELR, 2, 2),
192 MUX_CFG(MUX_DCMIPP, dcmipp_src, RCC_DCMIPPCKSELR, 0, 2),
193 MUX_CFG(MUX_ETH1, eth12_src, RCC_ETH12CKSELR, 0, 2),
194 MUX_CFG(MUX_ETH2, eth12_src, RCC_ETH12CKSELR, 8, 2),
195 MUX_CFG(MUX_FDCAN, fdcan_src, RCC_FDCANCKSELR, 0, 2),
196 MUX_CFG(MUX_FMC, fmc_src, RCC_FMCCKSELR, 0, 2),
197 MUX_CFG(MUX_I2C3, i2c345_src, RCC_I2C345CKSELR, 0, 3),
198 MUX_CFG(MUX_I2C4, i2c345_src, RCC_I2C345CKSELR, 3, 3),
199 MUX_CFG(MUX_I2C5, i2c345_src, RCC_I2C345CKSELR, 6, 3),
200 MUX_CFG(MUX_LPTIM1, lptim1_src, RCC_LPTIM1CKSELR, 0, 3),
201 MUX_CFG(MUX_LPTIM2, lptim23_src, RCC_LPTIM23CKSELR, 0, 3),
202 MUX_CFG(MUX_LPTIM3, lptim23_src, RCC_LPTIM23CKSELR, 3, 3),
203 MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 3),
204 MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 3),
205 MUX_CFG(MUX_QSPI, qspi_src, RCC_QSPICKSELR, 0, 2),
206 MUX_CFG(MUX_RNG1, rng1_src, RCC_RNG1CKSELR, 0, 2),
207 MUX_CFG(MUX_SAES, saes_src, RCC_SAESCKSELR, 0, 2),
208 MUX_CFG(MUX_SAI1, sai1_src, RCC_SAI1CKSELR, 0, 3),
209 MUX_CFG(MUX_SAI2, sai2_src, RCC_SAI2CKSELR, 0, 3),
210 MUX_CFG(MUX_SDMMC1, sdmmc12_src, RCC_SDMMC12CKSELR, 0, 3),
211 MUX_CFG(MUX_SDMMC2, sdmmc12_src, RCC_SDMMC12CKSELR, 3, 3),
212 MUX_CFG(MUX_SPDIF, spdif_src, RCC_SPDIFCKSELR, 0, 2),
213 MUX_CFG(MUX_SPI1, spi123_src, RCC_SPI2S1CKSELR, 0, 3),
214 MUX_CFG(MUX_SPI4, spi4_src, RCC_SPI45CKSELR, 0, 3),
215 MUX_CFG(MUX_SPI5, spi5_src, RCC_SPI45CKSELR, 3, 3),
216 MUX_CFG(MUX_STGEN, stgen_src, RCC_STGENCKSELR, 0, 2),
217 MUX_CFG(MUX_UART1, usart12_src, RCC_UART12CKSELR, 0, 3),
218 MUX_CFG(MUX_UART2, usart12_src, RCC_UART12CKSELR, 3, 3),
219 MUX_CFG(MUX_UART4, usart34578_src, RCC_UART4CKSELR, 0, 3),
220 MUX_CFG(MUX_UART6, usart6_src, RCC_UART6CKSELR, 0, 3),
221 MUX_CFG(MUX_USBO, usbo_src, RCC_USBCKSELR, 4, 1),
222 MUX_CFG(MUX_USBPHY, usbphy_src, RCC_USBCKSELR, 0, 2),
223 };
224
225 enum enum_gate_cfg {
226 GATE_ZERO, /* reserved for no gate */
227 GATE_MCO1,
228 GATE_MCO2,
229 GATE_DBGCK,
230 GATE_TRACECK,
231 GATE_DDRC1,
232 GATE_DDRC1LP,
233 GATE_DDRPHYC,
234 GATE_DDRPHYCLP,
235 GATE_DDRCAPB,
236 GATE_DDRCAPBLP,
237 GATE_AXIDCG,
238 GATE_DDRPHYCAPB,
239 GATE_DDRPHYCAPBLP,
240 GATE_TIM2,
241 GATE_TIM3,
242 GATE_TIM4,
243 GATE_TIM5,
244 GATE_TIM6,
245 GATE_TIM7,
246 GATE_LPTIM1,
247 GATE_SPI2,
248 GATE_SPI3,
249 GATE_USART3,
250 GATE_UART4,
251 GATE_UART5,
252 GATE_UART7,
253 GATE_UART8,
254 GATE_I2C1,
255 GATE_I2C2,
256 GATE_SPDIF,
257 GATE_TIM1,
258 GATE_TIM8,
259 GATE_SPI1,
260 GATE_USART6,
261 GATE_SAI1,
262 GATE_SAI2,
263 GATE_DFSDM,
264 GATE_ADFSDM,
265 GATE_FDCAN,
266 GATE_LPTIM2,
267 GATE_LPTIM3,
268 GATE_LPTIM4,
269 GATE_LPTIM5,
270 GATE_VREF,
271 GATE_DTS,
272 GATE_PMBCTRL,
273 GATE_HDP,
274 GATE_SYSCFG,
275 GATE_DCMIPP,
276 GATE_DDRPERFM,
277 GATE_IWDG2APB,
278 GATE_USBPHY,
279 GATE_STGENRO,
280 GATE_LTDC,
281 GATE_TZC,
282 GATE_ETZPC,
283 GATE_IWDG1APB,
284 GATE_BSEC,
285 GATE_STGENC,
286 GATE_USART1,
287 GATE_USART2,
288 GATE_SPI4,
289 GATE_SPI5,
290 GATE_I2C3,
291 GATE_I2C4,
292 GATE_I2C5,
293 GATE_TIM12,
294 GATE_TIM13,
295 GATE_TIM14,
296 GATE_TIM15,
297 GATE_TIM16,
298 GATE_TIM17,
299 GATE_DMA1,
300 GATE_DMA2,
301 GATE_DMAMUX1,
302 GATE_DMA3,
303 GATE_DMAMUX2,
304 GATE_ADC1,
305 GATE_ADC2,
306 GATE_USBO,
307 GATE_TSC,
308 GATE_GPIOA,
309 GATE_GPIOB,
310 GATE_GPIOC,
311 GATE_GPIOD,
312 GATE_GPIOE,
313 GATE_GPIOF,
314 GATE_GPIOG,
315 GATE_GPIOH,
316 GATE_GPIOI,
317 GATE_PKA,
318 GATE_SAES,
319 GATE_CRYP1,
320 GATE_HASH1,
321 GATE_RNG1,
322 GATE_BKPSRAM,
323 GATE_AXIMC,
324 GATE_MCE,
325 GATE_ETH1CK,
326 GATE_ETH1TX,
327 GATE_ETH1RX,
328 GATE_ETH1MAC,
329 GATE_FMC,
330 GATE_QSPI,
331 GATE_SDMMC1,
332 GATE_SDMMC2,
333 GATE_CRC1,
334 GATE_USBH,
335 GATE_ETH2CK,
336 GATE_ETH2TX,
337 GATE_ETH2RX,
338 GATE_ETH2MAC,
339 GATE_ETH1STP,
340 GATE_ETH2STP,
341 GATE_MDMA
342 };
343
344 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \
345 [id] = { \
346 .reg_off = (_offset), \
347 .bit_idx = (_bit_idx), \
348 .set_clr = (_offset_clr), \
349 }
350
351 static const struct stm32_gate_cfg stm32mp13_gates[] = {
352 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0),
353 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0),
354 GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0),
355 GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0),
356 GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0),
357 GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0),
358 GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0),
359 GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0),
360 GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0),
361 GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0),
362 GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0),
363 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0),
364 GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0),
365 GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1),
366 GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1),
367 GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1),
368 GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1),
369 GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1),
370 GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1),
371 GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1),
372 GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1),
373 GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1),
374 GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1),
375 GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1),
376 GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1),
377 GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1),
378 GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1),
379 GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1),
380 GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1),
381 GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1),
382 GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1),
383 GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1),
384 GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1),
385 GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1),
386 GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1),
387 GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1),
388 GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1),
389 GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1),
390 GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1),
391 GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1),
392 GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1),
393 GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1),
394 GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1),
395 GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1),
396 GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1),
397 GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1),
398 GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1),
399 GATE_CFG(GATE_SYSCFG, RCC_MP_NS_APB3ENSETR, 0, 1),
400 GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1),
401 GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1),
402 GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1),
403 GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1),
404 GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1),
405 GATE_CFG(GATE_LTDC, RCC_MP_NS_APB4ENSETR, 0, 1),
406 GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1),
407 GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1),
408 GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1),
409 GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1),
410 GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1),
411 GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1),
412 GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1),
413 GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1),
414 GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1),
415 GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1),
416 GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1),
417 GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1),
418 GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1),
419 GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1),
420 GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1),
421 GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1),
422 GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1),
423 GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1),
424 GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1),
425 GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1),
426 GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1),
427 GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1),
428 GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1),
429 GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1),
430 GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1),
431 GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1),
432 GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1),
433 GATE_CFG(GATE_GPIOA, RCC_MP_NS_AHB4ENSETR, 0, 1),
434 GATE_CFG(GATE_GPIOB, RCC_MP_NS_AHB4ENSETR, 1, 1),
435 GATE_CFG(GATE_GPIOC, RCC_MP_NS_AHB4ENSETR, 2, 1),
436 GATE_CFG(GATE_GPIOD, RCC_MP_NS_AHB4ENSETR, 3, 1),
437 GATE_CFG(GATE_GPIOE, RCC_MP_NS_AHB4ENSETR, 4, 1),
438 GATE_CFG(GATE_GPIOF, RCC_MP_NS_AHB4ENSETR, 5, 1),
439 GATE_CFG(GATE_GPIOG, RCC_MP_NS_AHB4ENSETR, 6, 1),
440 GATE_CFG(GATE_GPIOH, RCC_MP_NS_AHB4ENSETR, 7, 1),
441 GATE_CFG(GATE_GPIOI, RCC_MP_NS_AHB4ENSETR, 8, 1),
442 GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1),
443 GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1),
444 GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1),
445 GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1),
446 GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1),
447 GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1),
448 GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1),
449 GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1),
450 GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1),
451 GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1),
452 GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1),
453 GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1),
454 GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1),
455 GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1),
456 GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1),
457 GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1),
458 GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1),
459 GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1),
460 GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1),
461 GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1),
462 GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1),
463 GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1),
464 GATE_CFG(GATE_ETH1STP, RCC_MP_AHB6LPENSETR, 11, 1),
465 GATE_CFG(GATE_ETH2STP, RCC_MP_AHB6LPENSETR, 31, 1),
466 GATE_CFG(GATE_MDMA, RCC_MP_NS_AHB6ENSETR, 0, 1),
467 };
468
469 static const struct clk_div_table ck_trace_div_table[] = {
470 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
471 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
472 { 0 },
473 };
474
475 enum enum_div_cfg {
476 DIV_MCO1,
477 DIV_MCO2,
478 DIV_TRACE,
479 DIV_ETH1PTP,
480 DIV_ETH2PTP,
481 LAST_DIV
482 };
483
484 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \
485 [id] = { \
486 .reg_off = _offset, \
487 .shift = _shift, \
488 .width = _width, \
489 .div_flags = _flags, \
490 .table = _table, \
491 }
492
493 static const struct stm32_div_cfg stm32mp13_dividers[LAST_DIV] = {
494 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL),
495 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL),
496 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table),
497 DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL),
498 DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL),
499 };
500
501 struct clk_stm32_securiy {
502 u16 offset;
503 u8 bit_idx;
504 };
505
506 enum securit_clk {
507 SECF_NONE,
508 SECF_LPTIM2,
509 SECF_LPTIM3,
510 SECF_VREF,
511 SECF_DCMIPP,
512 SECF_USBPHY,
513 SECF_RTC,
514 SECF_TZC,
515 SECF_ETZPC,
516 SECF_IWDG1,
517 SECF_BSEC,
518 SECF_STGENC,
519 SECF_STGENRO,
520 SECF_USART1,
521 SECF_USART2,
522 SECF_SPI4,
523 SECF_SPI5,
524 SECF_I2C3,
525 SECF_I2C4,
526 SECF_I2C5,
527 SECF_TIM12,
528 SECF_TIM13,
529 SECF_TIM14,
530 SECF_TIM15,
531 SECF_TIM16,
532 SECF_TIM17,
533 SECF_DMA3,
534 SECF_DMAMUX2,
535 SECF_ADC1,
536 SECF_ADC2,
537 SECF_USBO,
538 SECF_TSC,
539 SECF_PKA,
540 SECF_SAES,
541 SECF_CRYP1,
542 SECF_HASH1,
543 SECF_RNG1,
544 SECF_BKPSRAM,
545 SECF_MCE,
546 SECF_FMC,
547 SECF_QSPI,
548 SECF_SDMMC1,
549 SECF_SDMMC2,
550 SECF_ETH1CK,
551 SECF_ETH1TX,
552 SECF_ETH1RX,
553 SECF_ETH1MAC,
554 SECF_ETH1STP,
555 SECF_ETH2CK,
556 SECF_ETH2TX,
557 SECF_ETH2RX,
558 SECF_ETH2MAC,
559 SECF_ETH2STP,
560 SECF_MCO1,
561 SECF_MCO2
562 };
563
564 #define SECF(_sec_id, _offset, _bit_idx) \
565 [_sec_id] = { \
566 .offset = _offset, \
567 .bit_idx = _bit_idx, \
568 }
569
570 static const struct clk_stm32_securiy stm32mp13_security[] = {
571 SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
572 SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
573 SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
574 SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
575 SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
576 SECF(SECF_RTC, RCC_APB5SECSR, RCC_APB5SECSR_RTCSECF),
577 SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
578 SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
579 SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
580 SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
581 SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
582 SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
583 SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
584 SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
585 SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
586 SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
587 SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
588 SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
589 SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
590 SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
591 SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
592 SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
593 SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
594 SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
595 SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
596 SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
597 SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
598 SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
599 SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
600 SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
601 SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
602 SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
603 SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
604 SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
605 SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
606 SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
607 SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
608 SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
609 SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
610 SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
611 SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
612 SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
613 SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
614 SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
615 SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
616 SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
617 SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
618 SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
619 SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
620 SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
621 SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
622 SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
623 SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SECF),
624 SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SECF),
625 };
626
627 #define PCLK(_id, _name, _parent, _flags, _gate_id, _sec_id) \
628 STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id)
629
630 #define TIMER(_id, _name, _parent, _flags, _gate_id, _sec_id) \
631 STM32_GATE(_id, _name, _parent, ((_flags) | CLK_SET_RATE_PARENT), \
632 _gate_id, _sec_id)
633
634 #define KCLK(_id, _name, _flags, _gate_id, _mux_id, _sec_id) \
635 STM32_COMPOSITE(_id, _name, _flags, _sec_id, \
636 _gate_id, _mux_id, NO_STM32_DIV)
637
638 static const struct clock_config stm32mp13_clock_cfg[] = {
639 TIMER(TIM2_K, "tim2_k", "timg1_ck", 0, GATE_TIM2, SECF_NONE),
640 TIMER(TIM3_K, "tim3_k", "timg1_ck", 0, GATE_TIM3, SECF_NONE),
641 TIMER(TIM4_K, "tim4_k", "timg1_ck", 0, GATE_TIM4, SECF_NONE),
642 TIMER(TIM5_K, "tim5_k", "timg1_ck", 0, GATE_TIM5, SECF_NONE),
643 TIMER(TIM6_K, "tim6_k", "timg1_ck", 0, GATE_TIM6, SECF_NONE),
644 TIMER(TIM7_K, "tim7_k", "timg1_ck", 0, GATE_TIM7, SECF_NONE),
645 TIMER(TIM1_K, "tim1_k", "timg2_ck", 0, GATE_TIM1, SECF_NONE),
646 TIMER(TIM8_K, "tim8_k", "timg2_ck", 0, GATE_TIM8, SECF_NONE),
647 TIMER(TIM12_K, "tim12_k", "timg3_ck", 0, GATE_TIM12, SECF_TIM12),
648 TIMER(TIM13_K, "tim13_k", "timg3_ck", 0, GATE_TIM13, SECF_TIM13),
649 TIMER(TIM14_K, "tim14_k", "timg3_ck", 0, GATE_TIM14, SECF_TIM14),
650 TIMER(TIM15_K, "tim15_k", "timg3_ck", 0, GATE_TIM15, SECF_TIM15),
651 TIMER(TIM16_K, "tim16_k", "timg3_ck", 0, GATE_TIM16, SECF_TIM16),
652 TIMER(TIM17_K, "tim17_k", "timg3_ck", 0, GATE_TIM17, SECF_TIM17),
653
654 /* Peripheral clocks */
655 PCLK(SYSCFG, "syscfg", "pclk3", 0, GATE_SYSCFG, SECF_NONE),
656 PCLK(VREF, "vref", "pclk3", 0, GATE_VREF, SECF_VREF),
657 PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, GATE_PMBCTRL, SECF_NONE),
658 PCLK(HDP, "hdp", "pclk3", 0, GATE_HDP, SECF_NONE),
659 PCLK(IWDG2, "iwdg2", "pclk4", 0, GATE_IWDG2APB, SECF_NONE),
660 PCLK(STGENRO, "stgenro", "pclk4", 0, GATE_STGENRO, SECF_STGENRO),
661 PCLK(TZPC, "tzpc", "pclk5", 0, GATE_TZC, SECF_TZC),
662 PCLK(IWDG1, "iwdg1", "pclk5", 0, GATE_IWDG1APB, SECF_IWDG1),
663 PCLK(BSEC, "bsec", "pclk5", 0, GATE_BSEC, SECF_BSEC),
664 PCLK(DMA1, "dma1", "ck_mlahb", 0, GATE_DMA1, SECF_NONE),
665 PCLK(DMA2, "dma2", "ck_mlahb", 0, GATE_DMA2, SECF_NONE),
666 PCLK(DMAMUX1, "dmamux1", "ck_mlahb", 0, GATE_DMAMUX1, SECF_NONE),
667 PCLK(DMAMUX2, "dmamux2", "ck_mlahb", 0, GATE_DMAMUX2, SECF_DMAMUX2),
668 PCLK(ADC1, "adc1", "ck_mlahb", 0, GATE_ADC1, SECF_ADC1),
669 PCLK(ADC2, "adc2", "ck_mlahb", 0, GATE_ADC2, SECF_ADC2),
670 PCLK(GPIOA, "gpioa", "pclk4", 0, GATE_GPIOA, SECF_NONE),
671 PCLK(GPIOB, "gpiob", "pclk4", 0, GATE_GPIOB, SECF_NONE),
672 PCLK(GPIOC, "gpioc", "pclk4", 0, GATE_GPIOC, SECF_NONE),
673 PCLK(GPIOD, "gpiod", "pclk4", 0, GATE_GPIOD, SECF_NONE),
674 PCLK(GPIOE, "gpioe", "pclk4", 0, GATE_GPIOE, SECF_NONE),
675 PCLK(GPIOF, "gpiof", "pclk4", 0, GATE_GPIOF, SECF_NONE),
676 PCLK(GPIOG, "gpiog", "pclk4", 0, GATE_GPIOG, SECF_NONE),
677 PCLK(GPIOH, "gpioh", "pclk4", 0, GATE_GPIOH, SECF_NONE),
678 PCLK(GPIOI, "gpioi", "pclk4", 0, GATE_GPIOI, SECF_NONE),
679 PCLK(TSC, "tsc", "pclk4", 0, GATE_TSC, SECF_TZC),
680 PCLK(PKA, "pka", "ck_axi", 0, GATE_PKA, SECF_PKA),
681 PCLK(CRYP1, "cryp1", "ck_axi", 0, GATE_CRYP1, SECF_CRYP1),
682 PCLK(HASH1, "hash1", "ck_axi", 0, GATE_HASH1, SECF_HASH1),
683 PCLK(BKPSRAM, "bkpsram", "ck_axi", 0, GATE_BKPSRAM, SECF_BKPSRAM),
684 PCLK(MDMA, "mdma", "ck_axi", 0, GATE_MDMA, SECF_NONE),
685 PCLK(ETH1TX, "eth1tx", "ck_axi", 0, GATE_ETH1TX, SECF_ETH1TX),
686 PCLK(ETH1RX, "eth1rx", "ck_axi", 0, GATE_ETH1RX, SECF_ETH1RX),
687 PCLK(ETH1MAC, "eth1mac", "ck_axi", 0, GATE_ETH1MAC, SECF_ETH1MAC),
688 PCLK(ETH2TX, "eth2tx", "ck_axi", 0, GATE_ETH2TX, SECF_ETH2TX),
689 PCLK(ETH2RX, "eth2rx", "ck_axi", 0, GATE_ETH2RX, SECF_ETH2RX),
690 PCLK(ETH2MAC, "eth2mac", "ck_axi", 0, GATE_ETH2MAC, SECF_ETH2MAC),
691 PCLK(CRC1, "crc1", "ck_axi", 0, GATE_CRC1, SECF_NONE),
692 PCLK(USBH, "usbh", "ck_axi", 0, GATE_USBH, SECF_NONE),
693 PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, GATE_DDRPERFM, SECF_NONE),
694 PCLK(ETH1STP, "eth1stp", "ck_axi", 0, GATE_ETH1STP, SECF_ETH1STP),
695 PCLK(ETH2STP, "eth2stp", "ck_axi", 0, GATE_ETH2STP, SECF_ETH2STP),
696
697 /* Kernel clocks */
698 KCLK(SDMMC1_K, "sdmmc1_k", 0, GATE_SDMMC1, MUX_SDMMC1, SECF_SDMMC1),
699 KCLK(SDMMC2_K, "sdmmc2_k", 0, GATE_SDMMC2, MUX_SDMMC2, SECF_SDMMC2),
700 KCLK(FMC_K, "fmc_k", 0, GATE_FMC, MUX_FMC, SECF_FMC),
701 KCLK(QSPI_K, "qspi_k", 0, GATE_QSPI, MUX_QSPI, SECF_QSPI),
702 KCLK(SPI2_K, "spi2_k", 0, GATE_SPI2, MUX_SPI23, SECF_NONE),
703 KCLK(SPI3_K, "spi3_k", 0, GATE_SPI3, MUX_SPI23, SECF_NONE),
704 KCLK(I2C1_K, "i2c1_k", 0, GATE_I2C1, MUX_I2C12, SECF_NONE),
705 KCLK(I2C2_K, "i2c2_k", 0, GATE_I2C2, MUX_I2C12, SECF_NONE),
706 KCLK(LPTIM4_K, "lptim4_k", 0, GATE_LPTIM4, MUX_LPTIM45, SECF_NONE),
707 KCLK(LPTIM5_K, "lptim5_k", 0, GATE_LPTIM5, MUX_LPTIM45, SECF_NONE),
708 KCLK(USART3_K, "usart3_k", 0, GATE_USART3, MUX_UART35, SECF_NONE),
709 KCLK(UART5_K, "uart5_k", 0, GATE_UART5, MUX_UART35, SECF_NONE),
710 KCLK(UART7_K, "uart7_k", 0, GATE_UART7, MUX_UART78, SECF_NONE),
711 KCLK(UART8_K, "uart8_k", 0, GATE_UART8, MUX_UART78, SECF_NONE),
712 KCLK(RNG1_K, "rng1_k", 0, GATE_RNG1, MUX_RNG1, SECF_RNG1),
713 KCLK(USBPHY_K, "usbphy_k", 0, GATE_USBPHY, MUX_USBPHY, SECF_USBPHY),
714 KCLK(STGEN_K, "stgen_k", 0, GATE_STGENC, MUX_STGEN, SECF_STGENC),
715 KCLK(SPDIF_K, "spdif_k", 0, GATE_SPDIF, MUX_SPDIF, SECF_NONE),
716 KCLK(SPI1_K, "spi1_k", 0, GATE_SPI1, MUX_SPI1, SECF_NONE),
717 KCLK(SPI4_K, "spi4_k", 0, GATE_SPI4, MUX_SPI4, SECF_SPI4),
718 KCLK(SPI5_K, "spi5_k", 0, GATE_SPI5, MUX_SPI5, SECF_SPI5),
719 KCLK(I2C3_K, "i2c3_k", 0, GATE_I2C3, MUX_I2C3, SECF_I2C3),
720 KCLK(I2C4_K, "i2c4_k", 0, GATE_I2C4, MUX_I2C4, SECF_I2C4),
721 KCLK(I2C5_K, "i2c5_k", 0, GATE_I2C5, MUX_I2C5, SECF_I2C5),
722 KCLK(LPTIM1_K, "lptim1_k", 0, GATE_LPTIM1, MUX_LPTIM1, SECF_NONE),
723 KCLK(LPTIM2_K, "lptim2_k", 0, GATE_LPTIM2, MUX_LPTIM2, SECF_LPTIM2),
724 KCLK(LPTIM3_K, "lptim3_k", 0, GATE_LPTIM3, MUX_LPTIM3, SECF_LPTIM3),
725 KCLK(USART1_K, "usart1_k", 0, GATE_USART1, MUX_UART1, SECF_USART1),
726 KCLK(USART2_K, "usart2_k", 0, GATE_USART2, MUX_UART2, SECF_USART2),
727 KCLK(UART4_K, "uart4_k", 0, GATE_UART4, MUX_UART4, SECF_NONE),
728 KCLK(USART6_K, "uart6_k", 0, GATE_USART6, MUX_UART6, SECF_NONE),
729 KCLK(FDCAN_K, "fdcan_k", 0, GATE_FDCAN, MUX_FDCAN, SECF_NONE),
730 KCLK(SAI1_K, "sai1_k", 0, GATE_SAI1, MUX_SAI1, SECF_NONE),
731 KCLK(SAI2_K, "sai2_k", 0, GATE_SAI2, MUX_SAI2, SECF_NONE),
732 KCLK(ADC1_K, "adc1_k", 0, GATE_ADC1, MUX_ADC1, SECF_ADC1),
733 KCLK(ADC2_K, "adc2_k", 0, GATE_ADC2, MUX_ADC2, SECF_ADC2),
734 KCLK(DCMIPP_K, "dcmipp_k", 0, GATE_DCMIPP, MUX_DCMIPP, SECF_DCMIPP),
735 KCLK(ADFSDM_K, "adfsdm_k", 0, GATE_ADFSDM, MUX_SAI1, SECF_NONE),
736 KCLK(USBO_K, "usbo_k", 0, GATE_USBO, MUX_USBO, SECF_USBO),
737 KCLK(ETH1CK_K, "eth1ck_k", 0, GATE_ETH1CK, MUX_ETH1, SECF_ETH1CK),
738 KCLK(ETH2CK_K, "eth2ck_k", 0, GATE_ETH2CK, MUX_ETH2, SECF_ETH2CK),
739 KCLK(SAES_K, "saes_k", 0, GATE_SAES, MUX_SAES, SECF_SAES),
740
741 STM32_GATE(DFSDM_K, "dfsdm_k", "ck_mlahb", 0, GATE_DFSDM, SECF_NONE),
742 STM32_GATE(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT,
743 GATE_LTDC, SECF_NONE),
744
745 STM32_GATE(DTS_K, "dts_k", "ck_lse", 0, GATE_DTS, SECF_NONE),
746
747 STM32_COMPOSITE(ETH1PTP_K, "eth1ptp_k", CLK_OPS_PARENT_ENABLE |
748 CLK_SET_RATE_NO_REPARENT, SECF_ETH1CK,
749 NO_STM32_GATE, MUX_ETH1, DIV_ETH1PTP),
750
751 STM32_COMPOSITE(ETH2PTP_K, "eth2ptp_k", CLK_OPS_PARENT_ENABLE |
752 CLK_SET_RATE_NO_REPARENT, SECF_ETH2CK,
753 NO_STM32_GATE, MUX_ETH2, DIV_ETH2PTP),
754
755 /* MCO clocks */
756 STM32_COMPOSITE(CK_MCO1, "ck_mco1", CLK_OPS_PARENT_ENABLE |
757 CLK_SET_RATE_NO_REPARENT, SECF_MCO1,
758 GATE_MCO1, MUX_MCO1, DIV_MCO1),
759
760 STM32_COMPOSITE(CK_MCO2, "ck_mco2", CLK_OPS_PARENT_ENABLE |
761 CLK_SET_RATE_NO_REPARENT, SECF_MCO2,
762 GATE_MCO2, MUX_MCO2, DIV_MCO2),
763
764 /* Debug clocks */
765 STM32_GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
766 GATE_DBGCK, SECF_NONE),
767
768 STM32_COMPOSITE_NOMUX(CK_TRACE, "ck_trace", "ck_axi",
769 CLK_OPS_PARENT_ENABLE, SECF_NONE,
770 GATE_TRACECK, DIV_TRACE),
771 };
772
stm32mp13_check_security(void __iomem * base,const struct clock_config * cfg)773 static int stm32mp13_check_security(void __iomem *base,
774 const struct clock_config *cfg)
775 {
776 int sec_id = cfg->sec_id;
777 int secured = 0;
778
779 if (sec_id != SECF_NONE) {
780 const struct clk_stm32_securiy *secf;
781
782 secf = &stm32mp13_security[sec_id];
783 secured = !!(readl(base + secf->offset) & BIT(secf->bit_idx));
784 }
785
786 return secured;
787 }
788
789 static const struct stm32_clock_match_data stm32mp13_data = {
790 .tab_clocks = stm32mp13_clock_cfg,
791 .num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
792 .clock_data = &(const struct clk_stm32_clock_data) {
793 .num_gates = ARRAY_SIZE(stm32mp13_gates),
794 .gates = stm32mp13_gates,
795 .muxes = stm32mp13_muxes,
796 .dividers = stm32mp13_dividers,
797 },
798 .check_security = stm32mp13_check_security,
799 };
800
stm32mp1_clk_probe(struct udevice * dev)801 static int stm32mp1_clk_probe(struct udevice *dev)
802 {
803 struct udevice *scmi;
804 int err;
805
806 /* force SCMI probe to register all SCMI clocks */
807 uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi);
808
809 err = stm32_rcc_init(dev, &stm32mp13_data);
810 if (err)
811 return err;
812
813 gd->cpu_clk = clk_stm32_get_rate_by_name("ck_mpu");
814 gd->bus_clk = clk_stm32_get_rate_by_name("ck_axi");
815
816 /* DDRPHYC father */
817 gd->mem_clk = clk_stm32_get_rate_by_name("pll2_r");
818
819 if (IS_ENABLED(CONFIG_DISPLAY_CPUINFO)) {
820 if (gd->flags & GD_FLG_RELOC) {
821 char buf[32];
822
823 log_info("Clocks:\n");
824 log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
825 log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
826 log_info("- PER : %s MHz\n",
827 strmhz(buf, clk_stm32_get_rate_by_name("ck_per")));
828 log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
829 }
830 }
831
832 return 0;
833 }
834
835 U_BOOT_DRIVER(stm32mp1_clock) = {
836 .name = "stm32mp13_clk",
837 .id = UCLASS_CLK,
838 .ops = &stm32_clk_ops,
839 .priv_auto = sizeof(struct stm32mp_rcc_priv),
840 .probe = stm32mp1_clk_probe,
841 };
842