1 /* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved 4 * 5 * Configuration settings for the STM32MP13x CPU 6 */ 7 8 #ifndef STM32MP13_RCC_H 9 #define STM32MP13_RCC_H 10 11 /* RCC registers */ 12 #define RCC_SECCFGR 0x0 13 #define RCC_MP_SREQSETR 0x100 14 #define RCC_MP_SREQCLRR 0x104 15 #define RCC_MP_APRSTCR 0x108 16 #define RCC_MP_APRSTSR 0x10c 17 #define RCC_PWRLPDLYCR 0x110 18 #define RCC_MP_GRSTCSETR 0x114 19 #define RCC_BR_RSTSCLRR 0x118 20 #define RCC_MP_RSTSSETR 0x11c 21 #define RCC_MP_RSTSCLRR 0x120 22 #define RCC_MP_IWDGFZSETR 0x124 23 #define RCC_MP_IWDGFZCLRR 0x128 24 #define RCC_MP_CIER 0x200 25 #define RCC_MP_CIFR 0x204 26 #define RCC_BDCR 0x400 27 #define RCC_RDLSICR 0x404 28 #define RCC_OCENSETR 0x420 29 #define RCC_OCENCLRR 0x424 30 #define RCC_OCRDYR 0x428 31 #define RCC_HSICFGR 0x440 32 #define RCC_CSICFGR 0x444 33 #define RCC_MCO1CFGR 0x460 34 #define RCC_MCO2CFGR 0x464 35 #define RCC_DBGCFGR 0x468 36 #define RCC_RCK12SELR 0x480 37 #define RCC_RCK3SELR 0x484 38 #define RCC_RCK4SELR 0x488 39 #define RCC_PLL1CR 0x4a0 40 #define RCC_PLL1CFGR1 0x4a4 41 #define RCC_PLL1CFGR2 0x4a8 42 #define RCC_PLL1FRACR 0x4ac 43 #define RCC_PLL1CSGR 0x4b0 44 #define RCC_PLL2CR 0x4d0 45 #define RCC_PLL2CFGR1 0x4d4 46 #define RCC_PLL2CFGR2 0x4d8 47 #define RCC_PLL2FRACR 0x4dc 48 #define RCC_PLL2CSGR 0x4e0 49 #define RCC_PLL3CR 0x500 50 #define RCC_PLL3CFGR1 0x504 51 #define RCC_PLL3CFGR2 0x508 52 #define RCC_PLL3FRACR 0x50c 53 #define RCC_PLL3CSGR 0x510 54 #define RCC_PLL4CR 0x520 55 #define RCC_PLL4CFGR1 0x524 56 #define RCC_PLL4CFGR2 0x528 57 #define RCC_PLL4FRACR 0x52c 58 #define RCC_PLL4CSGR 0x530 59 #define RCC_MPCKSELR 0x540 60 #define RCC_ASSCKSELR 0x544 61 #define RCC_MSSCKSELR 0x548 62 #define RCC_CPERCKSELR 0x54c 63 #define RCC_RTCDIVR 0x560 64 #define RCC_MPCKDIVR 0x564 65 #define RCC_AXIDIVR 0x568 66 #define RCC_MLAHBDIVR 0x56c 67 #define RCC_APB1DIVR 0x570 68 #define RCC_APB2DIVR 0x574 69 #define RCC_APB3DIVR 0x578 70 #define RCC_APB4DIVR 0x57c 71 #define RCC_APB5DIVR 0x580 72 #define RCC_APB6DIVR 0x584 73 #define RCC_TIMG1PRER 0x5a0 74 #define RCC_TIMG2PRER 0x5a4 75 #define RCC_TIMG3PRER 0x5a8 76 #define RCC_DDRITFCR 0x5c0 77 #define RCC_I2C12CKSELR 0x600 78 #define RCC_I2C345CKSELR 0x604 79 #define RCC_SPI2S1CKSELR 0x608 80 #define RCC_SPI2S23CKSELR 0x60c 81 #define RCC_SPI45CKSELR 0x610 82 #define RCC_UART12CKSELR 0x614 83 #define RCC_UART35CKSELR 0x618 84 #define RCC_UART4CKSELR 0x61c 85 #define RCC_UART6CKSELR 0x620 86 #define RCC_UART78CKSELR 0x624 87 #define RCC_LPTIM1CKSELR 0x628 88 #define RCC_LPTIM23CKSELR 0x62c 89 #define RCC_LPTIM45CKSELR 0x630 90 #define RCC_SAI1CKSELR 0x634 91 #define RCC_SAI2CKSELR 0x638 92 #define RCC_FDCANCKSELR 0x63c 93 #define RCC_SPDIFCKSELR 0x640 94 #define RCC_ADC12CKSELR 0x644 95 #define RCC_SDMMC12CKSELR 0x648 96 #define RCC_ETH12CKSELR 0x64c 97 #define RCC_USBCKSELR 0x650 98 #define RCC_QSPICKSELR 0x654 99 #define RCC_FMCCKSELR 0x658 100 #define RCC_RNG1CKSELR 0x65c 101 #define RCC_STGENCKSELR 0x660 102 #define RCC_DCMIPPCKSELR 0x664 103 #define RCC_SAESCKSELR 0x668 104 #define RCC_APB1RSTSETR 0x6a0 105 #define RCC_APB1RSTCLRR 0x6a4 106 #define RCC_APB2RSTSETR 0x6a8 107 #define RCC_APB2RSTCLRR 0x6ac 108 #define RCC_APB3RSTSETR 0x6b0 109 #define RCC_APB3RSTCLRR 0x6b4 110 #define RCC_APB4RSTSETR 0x6b8 111 #define RCC_APB4RSTCLRR 0x6bc 112 #define RCC_APB5RSTSETR 0x6c0 113 #define RCC_APB5RSTCLRR 0x6c4 114 #define RCC_APB6RSTSETR 0x6c8 115 #define RCC_APB6RSTCLRR 0x6cc 116 #define RCC_AHB2RSTSETR 0x6d0 117 #define RCC_AHB2RSTCLRR 0x6d4 118 #define RCC_AHB4RSTSETR 0x6e0 119 #define RCC_AHB4RSTCLRR 0x6e4 120 #define RCC_AHB5RSTSETR 0x6e8 121 #define RCC_AHB5RSTCLRR 0x6ec 122 #define RCC_AHB6RSTSETR 0x6f0 123 #define RCC_AHB6RSTCLRR 0x6f4 124 #define RCC_MP_APB1ENSETR 0x700 125 #define RCC_MP_APB1ENCLRR 0x704 126 #define RCC_MP_APB2ENSETR 0x708 127 #define RCC_MP_APB2ENCLRR 0x70c 128 #define RCC_MP_APB3ENSETR 0x710 129 #define RCC_MP_APB3ENCLRR 0x714 130 #define RCC_MP_S_APB3ENSETR 0x718 131 #define RCC_MP_S_APB3ENCLRR 0x71c 132 #define RCC_MP_NS_APB3ENSETR 0x720 133 #define RCC_MP_NS_APB3ENCLRR 0x724 134 #define RCC_MP_APB4ENSETR 0x728 135 #define RCC_MP_APB4ENCLRR 0x72c 136 #define RCC_MP_S_APB4ENSETR 0x730 137 #define RCC_MP_S_APB4ENCLRR 0x734 138 #define RCC_MP_NS_APB4ENSETR 0x738 139 #define RCC_MP_NS_APB4ENCLRR 0x73c 140 #define RCC_MP_APB5ENSETR 0x740 141 #define RCC_MP_APB5ENCLRR 0x744 142 #define RCC_MP_APB6ENSETR 0x748 143 #define RCC_MP_APB6ENCLRR 0x74c 144 #define RCC_MP_AHB2ENSETR 0x750 145 #define RCC_MP_AHB2ENCLRR 0x754 146 #define RCC_MP_AHB4ENSETR 0x760 147 #define RCC_MP_AHB4ENCLRR 0x764 148 #define RCC_MP_S_AHB4ENSETR 0x768 149 #define RCC_MP_S_AHB4ENCLRR 0x76c 150 #define RCC_MP_NS_AHB4ENSETR 0x770 151 #define RCC_MP_NS_AHB4ENCLRR 0x774 152 #define RCC_MP_AHB5ENSETR 0x778 153 #define RCC_MP_AHB5ENCLRR 0x77c 154 #define RCC_MP_AHB6ENSETR 0x780 155 #define RCC_MP_AHB6ENCLRR 0x784 156 #define RCC_MP_S_AHB6ENSETR 0x788 157 #define RCC_MP_S_AHB6ENCLRR 0x78c 158 #define RCC_MP_NS_AHB6ENSETR 0x790 159 #define RCC_MP_NS_AHB6ENCLRR 0x794 160 #define RCC_MP_APB1LPENSETR 0x800 161 #define RCC_MP_APB1LPENCLRR 0x804 162 #define RCC_MP_APB2LPENSETR 0x808 163 #define RCC_MP_APB2LPENCLRR 0x80c 164 #define RCC_MP_APB3LPENSETR 0x810 165 #define RCC_MP_APB3LPENCLRR 0x814 166 #define RCC_MP_S_APB3LPENSETR 0x818 167 #define RCC_MP_S_APB3LPENCLRR 0x81c 168 #define RCC_MP_NS_APB3LPENSETR 0x820 169 #define RCC_MP_NS_APB3LPENCLRR 0x824 170 #define RCC_MP_APB4LPENSETR 0x828 171 #define RCC_MP_APB4LPENCLRR 0x82c 172 #define RCC_MP_S_APB4LPENSETR 0x830 173 #define RCC_MP_S_APB4LPENCLRR 0x834 174 #define RCC_MP_NS_APB4LPENSETR 0x838 175 #define RCC_MP_NS_APB4LPENCLRR 0x83c 176 #define RCC_MP_APB5LPENSETR 0x840 177 #define RCC_MP_APB5LPENCLRR 0x844 178 #define RCC_MP_APB6LPENSETR 0x848 179 #define RCC_MP_APB6LPENCLRR 0x84c 180 #define RCC_MP_AHB2LPENSETR 0x850 181 #define RCC_MP_AHB2LPENCLRR 0x854 182 #define RCC_MP_AHB4LPENSETR 0x858 183 #define RCC_MP_AHB4LPENCLRR 0x85c 184 #define RCC_MP_S_AHB4LPENSETR 0x868 185 #define RCC_MP_S_AHB4LPENCLRR 0x86c 186 #define RCC_MP_NS_AHB4LPENSETR 0x870 187 #define RCC_MP_NS_AHB4LPENCLRR 0x874 188 #define RCC_MP_AHB5LPENSETR 0x878 189 #define RCC_MP_AHB5LPENCLRR 0x87c 190 #define RCC_MP_AHB6LPENSETR 0x880 191 #define RCC_MP_AHB6LPENCLRR 0x884 192 #define RCC_MP_S_AHB6LPENSETR 0x888 193 #define RCC_MP_S_AHB6LPENCLRR 0x88c 194 #define RCC_MP_NS_AHB6LPENSETR 0x890 195 #define RCC_MP_NS_AHB6LPENCLRR 0x894 196 #define RCC_MP_S_AXIMLPENSETR 0x898 197 #define RCC_MP_S_AXIMLPENCLRR 0x89c 198 #define RCC_MP_NS_AXIMLPENSETR 0x8a0 199 #define RCC_MP_NS_AXIMLPENCLRR 0x8a4 200 #define RCC_MP_MLAHBLPENSETR 0x8a8 201 #define RCC_MP_MLAHBLPENCLRR 0x8ac 202 #define RCC_APB3SECSR 0x8c0 203 #define RCC_APB4SECSR 0x8c4 204 #define RCC_APB5SECSR 0x8c8 205 #define RCC_APB6SECSR 0x8cc 206 #define RCC_AHB2SECSR 0x8d0 207 #define RCC_AHB4SECSR 0x8d4 208 #define RCC_AHB5SECSR 0x8d8 209 #define RCC_AHB6SECSR 0x8dc 210 #define RCC_VERR 0xff4 211 #define RCC_IDR 0xff8 212 #define RCC_SIDR 0xffc 213 214 /* RCC_SECCFGR register fields */ 215 #define RCC_SECCFGR_MCO1SECF 22 216 #define RCC_SECCFGR_MCO2SECF 23 217 218 /* RCC_APB3SECSR register fields */ 219 #define RCC_APB3SECSR_LPTIM2SECF 0 220 #define RCC_APB3SECSR_LPTIM3SECF 1 221 #define RCC_APB3SECSR_VREFSECF 13 222 223 /* RCC_APB4SECSR register fields */ 224 #define RCC_APB4SECSR_DCMIPPSECF 1 225 #define RCC_APB4SECSR_USBPHYSECF 16 226 227 /* RCC_APB5SECSR register fields */ 228 #define RCC_APB5SECSR_RTCSECF 8 229 #define RCC_APB5SECSR_TZCSECF 11 230 #define RCC_APB5SECSR_ETZPCSECF 13 231 #define RCC_APB5SECSR_IWDG1SECF 15 232 #define RCC_APB5SECSR_BSECSECF 16 233 #define RCC_APB5SECSR_STGENCSECF 20 234 #define RCC_APB5SECSR_STGENROSECF 21 235 236 /* RCC_APB6SECSR register fields */ 237 #define RCC_APB6SECSR_USART1SECF 0 238 #define RCC_APB6SECSR_USART2SECF 1 239 #define RCC_APB6SECSR_SPI4SECF 2 240 #define RCC_APB6SECSR_SPI5SECF 3 241 #define RCC_APB6SECSR_I2C3SECF 4 242 #define RCC_APB6SECSR_I2C4SECF 5 243 #define RCC_APB6SECSR_I2C5SECF 6 244 #define RCC_APB6SECSR_TIM12SECF 7 245 #define RCC_APB6SECSR_TIM13SECF 8 246 #define RCC_APB6SECSR_TIM14SECF 9 247 #define RCC_APB6SECSR_TIM15SECF 10 248 #define RCC_APB6SECSR_TIM16SECF 11 249 #define RCC_APB6SECSR_TIM17SECF 12 250 251 /* RCC_AHB2SECSR register fields */ 252 #define RCC_AHB2SECSR_DMA3SECF 3 253 #define RCC_AHB2SECSR_DMAMUX2SECF 4 254 #define RCC_AHB2SECSR_ADC1SECF 5 255 #define RCC_AHB2SECSR_ADC2SECF 6 256 #define RCC_AHB2SECSR_USBOSECF 8 257 258 /* RCC_AHB4SECSR register fields */ 259 #define RCC_AHB4SECSR_TSCSECF 15 260 261 /* RCC_AHB5SECSR register fields */ 262 #define RCC_AHB5SECSR_PKASECF 2 263 #define RCC_AHB5SECSR_SAESSECF 3 264 #define RCC_AHB5SECSR_CRYP1SECF 4 265 #define RCC_AHB5SECSR_HASH1SECF 5 266 #define RCC_AHB5SECSR_RNG1SECF 6 267 #define RCC_AHB5SECSR_BKPSRAMSECF 8 268 269 /* RCC_AHB6SECSR register fields */ 270 #define RCC_AHB6SECSR_MCESECF 1 271 #define RCC_AHB6SECSR_FMCSECF 12 272 #define RCC_AHB6SECSR_QSPISECF 14 273 #define RCC_AHB6SECSR_SDMMC1SECF 16 274 #define RCC_AHB6SECSR_SDMMC2SECF 17 275 276 #define RCC_AHB6SECSR_ETH1CKSECF 7 277 #define RCC_AHB6SECSR_ETH1TXSECF 8 278 #define RCC_AHB6SECSR_ETH1RXSECF 9 279 #define RCC_AHB6SECSR_ETH1MACSECF 10 280 #define RCC_AHB6SECSR_ETH1STPSECF 11 281 282 #define RCC_AHB6SECSR_ETH2CKSECF 27 283 #define RCC_AHB6SECSR_ETH2TXSECF 28 284 #define RCC_AHB6SECSR_ETH2RXSECF 29 285 #define RCC_AHB6SECSR_ETH2MACSECF 30 286 #define RCC_AHB6SECSR_ETH2STPSECF 31 287 288 #endif /* STM32MP13_RCC_H */ 289