1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (C) 2018 Amarula Solutions.
4  * Author: Jagan Teki <jagan@amarulasolutions.com>
5  */
6 
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <clk/sunxi.h>
12 #include <dt-bindings/clock/sun4i-a10-ccu.h>
13 #include <dt-bindings/reset/sun4i-a10-ccu.h>
14 #include <linux/bitops.h>
15 
16 static struct ccu_clk_gate a10_gates[] = {
17 	[CLK_AHB_OTG]		= GATE(0x060, BIT(0)),
18 	[CLK_AHB_EHCI0]		= GATE(0x060, BIT(1)),
19 	[CLK_AHB_OHCI0]		= GATE(0x060, BIT(2)),
20 	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
21 	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
22 	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
23 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
24 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
25 	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
26 	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
27 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
28 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
29 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
30 	[CLK_AHB_SPI2]		= GATE(0x060, BIT(22)),
31 	[CLK_AHB_SPI3]		= GATE(0x060, BIT(23)),
32 
33 	[CLK_AHB_GMAC]		= GATE(0x064, BIT(17)),
34 
35 	[CLK_APB0_PIO]		= GATE(0x068, BIT(5)),
36 
37 	[CLK_APB1_I2C0]		= GATE(0x06c, BIT(0)),
38 	[CLK_APB1_I2C1]		= GATE(0x06c, BIT(1)),
39 	[CLK_APB1_I2C2]		= GATE(0x06c, BIT(2)),
40 	[CLK_APB1_I2C3]		= GATE(0x06c, BIT(3)),
41 	[CLK_APB1_I2C4]		= GATE(0x06c, BIT(15)),
42 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
43 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
44 	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
45 	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
46 	[CLK_APB1_UART4]	= GATE(0x06c, BIT(20)),
47 	[CLK_APB1_UART5]	= GATE(0x06c, BIT(21)),
48 	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
49 	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
50 
51 	[CLK_NAND]		= GATE(0x080, BIT(31)),
52 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
53 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
54 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
55 
56 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(6)),
57 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(7)),
58 	[CLK_USB_PHY]		= GATE(0x0cc, BIT(8)),
59 
60 	[CLK_SPI3]		= GATE(0x0d4, BIT(31)),
61 };
62 
63 static struct ccu_reset a10_resets[] = {
64 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
65 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
66 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
67 };
68 
69 const struct ccu_desc a10_ccu_desc = {
70 	.gates = a10_gates,
71 	.resets = a10_resets,
72 	.num_gates = ARRAY_SIZE(a10_gates),
73 	.num_resets = ARRAY_SIZE(a10_resets),
74 };
75