1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (C) 2018 Amarula Solutions B.V. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <clk/sunxi.h> 12 #include <dt-bindings/clock/sun6i-a31-ccu.h> 13 #include <dt-bindings/reset/sun6i-a31-ccu.h> 14 #include <linux/bitops.h> 15 16 static struct ccu_clk_gate a31_gates[] = { 17 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), 18 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), 19 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), 20 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), 21 [CLK_AHB1_NAND1] = GATE(0x060, BIT(12)), 22 [CLK_AHB1_NAND0] = GATE(0x060, BIT(13)), 23 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), 24 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), 25 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)), 26 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)), 27 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)), 28 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), 29 [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), 30 [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)), 31 [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)), 32 [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), 33 [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), 34 35 [CLK_APB1_PIO] = GATE(0x068, BIT(5)), 36 37 [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), 38 [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), 39 [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), 40 [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)), 41 [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), 42 [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), 43 [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), 44 [CLK_APB2_UART3] = GATE(0x06c, BIT(19)), 45 [CLK_APB2_UART4] = GATE(0x06c, BIT(20)), 46 [CLK_APB2_UART5] = GATE(0x06c, BIT(21)), 47 48 [CLK_NAND0] = GATE(0x080, BIT(31)), 49 [CLK_NAND1] = GATE(0x084, BIT(31)), 50 [CLK_SPI0] = GATE(0x0a0, BIT(31)), 51 [CLK_SPI1] = GATE(0x0a4, BIT(31)), 52 [CLK_SPI2] = GATE(0x0a8, BIT(31)), 53 [CLK_SPI3] = GATE(0x0ac, BIT(31)), 54 55 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), 56 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), 57 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), 58 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), 59 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), 60 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), 61 }; 62 63 static struct ccu_reset a31_resets[] = { 64 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), 65 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), 66 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), 67 68 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)), 69 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), 70 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), 71 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), 72 [RST_AHB1_NAND1] = RESET(0x2c0, BIT(12)), 73 [RST_AHB1_NAND0] = RESET(0x2c0, BIT(13)), 74 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)), 75 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)), 76 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)), 77 [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)), 78 [RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)), 79 [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), 80 [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), 81 [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)), 82 [RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)), 83 [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)), 84 [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)), 85 86 [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)), 87 [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)), 88 [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)), 89 [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)), 90 [RST_APB2_UART0] = RESET(0x2d8, BIT(16)), 91 [RST_APB2_UART1] = RESET(0x2d8, BIT(17)), 92 [RST_APB2_UART2] = RESET(0x2d8, BIT(18)), 93 [RST_APB2_UART3] = RESET(0x2d8, BIT(19)), 94 [RST_APB2_UART4] = RESET(0x2d8, BIT(20)), 95 [RST_APB2_UART5] = RESET(0x2d8, BIT(21)), 96 }; 97 98 const struct ccu_desc a31_ccu_desc = { 99 .gates = a31_gates, 100 .resets = a31_resets, 101 .num_gates = ARRAY_SIZE(a31_gates), 102 .num_resets = ARRAY_SIZE(a31_resets), 103 }; 104